Static Timing Analysis Design Engineer

European Tech Recruit; Cork; On-site; EUR 90,000 - 110,000; Full time

Job summary

European Tech Recruit is partnering with a multinational semiconductor company based in Cork to hire an experienced Static Timing Analysis Design Engineer. You will perform STA, develop timing constraints, and optimize timing for high‑performance SOCs while collaborating with cross‑functional teams to assure timing closure and model validation.

In this role you will drive automation for timing data and contribute to project milestones within a fast-paced engineering environment in County Cork.

Qualifications

• Experience with STA tools for large SoCs
• Automation experience with scripting languages
• Strong knowledge of ASIC RTL-to-GDS flows

Responsibilities

• Perform STA and timing closure for complex cores and SOCs
• Develop timing constraints and optimize timing performance
• Drive accuracy of timing closure and signoff checks
• Automate timing and power data mining and processing
• Collaborate with cross-functional teams to ensure timing closure
• Validate timing models and datasets for production releases
• Contribute to project milestones and deliverables
• Resolve issues to ensure smooth project execution

Skills

STA expertise

Python scripting

TCL scripting

ASIC design flows

Communication

Tools

PrimeTime

PrimeShield

Tempus

PTECO

Tempus ECO

Job description

Static Timing Analysis Design Engineer

European Tech Recruit are working closely with a multinational semiconductor technology company, based in Cork, who are looking for an experienced Static Timing Analysis Design Engineer to join their team.

As an STA Engineer, you will perform static timing analysis, develop timing constraints, and optimize timing performance for a variety of high-performance, high-quality, low-power world-class products. You will collaborate with cross-functional teams to ensure timing closure and validate timing models, contributing to the successful execution of product development.

Responsibilities as Static Timing Analysis Design Engineer:

• Performing STA and timing closure for complex cores and full-chip SOCs.
• Enhancing techniques and methodologies for STA and timing closure.
• Driving accuracy of timing closure and static/dynamic flows to reduce turnaround time.
• Ensuring compliance with timing signoff checklists and criteria.
• Automation for timing and power data mining and processing.
• Participating in project proposal development including key milestones and deliverables.
• Executing and delivering project goals in a timely manner with production support.
• Resolving issues in all phases of development to ensure smooth project execution.

Requirements:

• Expertise in STA tools (PrimeTime, PrimeShield or Tempus) used for hierarchical analysis in large SoCs.
• Hands-on experience with Tweaker, PrimeClosure, PTECO, or Tempus ECO for timing closure.
• Highly proficient in automation: Python, TCL or Perl.
• Strong knowledge of ASIC design flows (RTL-to-GDS).
• Interest in Design for Parametric Yield is an added advantage.
• Comfortable with extraction, circuit simulation tools and environments is a plus.
• Excellent problem-solving skills and result-driven approach, able to work and drive practical solutions under research environment.
• Good communication and personal skills in a multi-disciplinary, fast-paced engineering environment.

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