Senior Timing Engineer

European Tech Recruit; Cork; On-site; EUR 65,000 - 90,000; Full time

Job summary

European Tech Recruit seeks an experienced ASIC Engineer to drive timing methodologies across ASIC/SoC projects. You will characterise standard-cell libraries, correlate EDA tool results with SPICE simulations and collaborate across hardware, software and design teams.

Responsibilities include RTL-to-GDS support, flow automation with Python/Tcl/Bash, and SPICE modelling for ageing and reliability on advanced nodes. A Master’s degree and 3+ years of relevant experience are expected.

Qualifications

• Master’s degree or higher in Electrical/Electronic/Computer Engineering, CS or related.
• At least three years in ASIC design, verification, validation, integration or related engineering work.
• Two+ years with architecture and design tools.
• Two+ years scripting or programming experience.
• Two+ years experience with design-verification methods.
• Experience with timing analysis and standard-cell library characterisation.
• Exposure to LVF, AOCV, POCV or SOCV in timing sign-off.

Responsibilities

• Develop, optimise and validate timing methodologies for ASIC/SoC designs.
• Characterise standard-cell libraries and correlate with SPICE simulations.
• Support RTL-to-GDS and layout workflows using EDA tools.
• Create circuit specs, designs, architectures and system-level simulations.
• Automate engineering processes and develop new flows with scripting languages.
• Produce documentation for ASIC, IP and EDA projects.

Skills

Timing analysis

Library characterization

Scripting languages

SPICE modelling

EDA workflows

Variation methodologies LVF/AOCV/POCV

Ageing/reliability modelling

Education

Master’s degree in Electrical/Electronic/Computer Engineering or CS

Tools

Cadence tools

SPICE simulators

Job description

A leading technology organisation is seeking an experienced ASIC Engineer to support the development of high-performance, energy-efficient semiconductor products. You will work across IP blocks and SoCs, contributing to their definition, modelling, design, optimisation, verification, validation and implementation.

This position offers the opportunity to shape advanced timing and characterisation methodologies while collaborating with hardware, software and design teams throughout the development lifecycle.

Your Responsibilities

• Develop, optimise and validate timing methodologies for advanced ASIC and SoC designs.
• Perform standard-cell library characterisation and work with LVF, AOCV, POCV and SOCV methodologies.
• Correlate timing sign-off tools with SPICE simulations across timing, noise, Monte Carlo analysis and related metrics.
• Assess design flows spanning synthesis, place and route, static timing analysis, power analysis and verification.
• Create circuit specifications, logic designs, architectures and system-level simulations.
• Support RTL-to-GDS and custom circuit design and layout workflows using relevant EDA tools.
• Collaborate with cross-functional engineering teams to define implementation strategies that meet system and product requirements.
• Automate engineering processes and develop new flows using Python, Perl, Tcl, Bash or comparable scripting languages.
• Contribute to SPICE extraction and modelling, including ageing and reliability considerations for advanced process nodes.
• Investigate, develop and validate new design and sign-off methodologies.
• Produce clear, detailed documentation for ASIC, IP and EDA projects.

What We’re Looking For

• Substantial experience with semiconductor timing activities, including library characterisation and statistical variation methodologies such as LVF, AOCV, POCV or SOCV.
• Hands-on experience characterising standard-cell libraries.
• Strong understanding of timing sign-off and the correlation of EDA tool results with SPICE simulation.
• Strong scripting and workflow-automation skills using Python, Perl, Tcl, Bash or similar technologies.
• Knowledge of SPICE extraction, device modelling and ageing or reliability models for advanced technology nodes.
• Sound knowledge of modern physical-design practices, including place and route and static timing analysis sign-off.
• A proactive approach to learning and developing new engineering methodologies.
• Master’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science or a related discipline.
• At least three years of experience in ASIC design, verification, validation, integration or related engineering work.
• Two or more years of experience using architecture and design tools.
• Two or more years of scripting or programming experience.
• Two or more years of experience with design-verification methods.

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