Sr Timing Engineer

European Tech Recruit; Munster; On-site; EUR 70,000 - 100,000; Full time

Job summary

European Tech Recruit is seeking a Senior Timing Engineer for Ireland with relocation package offered. You will develop, optimise and validate timing methodologies focused on standard-cell library characterisation, timing models, variation-aware timing and sign-off flows.

You will also automate engineering flows using Python, Perl, TCL and Bash, work with SPICE extraction and aging/reliability models, and collaborate with physical design teams to support STA and timing closure.

Qualifications

• Experience in ASIC timing and sign-off workflows.
• Hands-on standard-cell library characterisation experience.
• Strong knowledge of timing variation methodologies.
• Experience with SPICE simulations and aging models.

Responsibilities

• Develop and optimise timing methodologies for standard-cell libraries.
• Perform library characterisation and flow improvements.
• Correlate results between timing sign-off tools and SPICE.
• Evaluate timing, noise, Monte Carlo and variation analyses.
• Automate engineering flows using Python, Perl, TCL, Bash.
• Collaborate with P&R and STA teams to reach timing closure.

Skills

Timing methodologies

Sign-off

Standard-cell characterisation

LVF/AOCV/POCV/SOCV

SPICE simulations

EDA/CAD tools

Python

Perl

TCL

Bash

Aging/reliability models

STA

P&R collaboration

Education

Master's degree in Electrical Engineering or related field

Tools

EDA tools

ASIC design tools

SPICE extraction tooling

Job description

Senior Timing Engineer - Ireland - Relocation Package Offered

You will be responsible for developing, optimising and validating timing methodologies, with a particular focus on standard-cell library characterisation, timing models, variation-aware timing and sign-off flows.

What You'll Be Doing

• Develop and optimise timing-related methodologies covering standard-cell libraries, LVF and variation-aware timing models.
• Perform and improve library characterisation processes and flows.
• Analyse and correlate results between different timing sign-off tools and SPICE simulations.
• Evaluate timing, noise, Monte Carlo, process/voltage/temperature and other relevant metrics.
• Develop and automate engineering flows using Python, Perl, TCL and Bash.
• Work with SPICE extraction, modelling and aging/reliability models for advanced technology nodes.
• Support and improve Static Timing Analysis (STA) and timing sign-off methodologies.
• Collaborate with physical design teams across synthesis, place and route (P&R) and timing closure.

What We're Looking For

• Strong professional experience in semiconductor timing methodologies and sign-off.
• Hands-on experience with standard-cell library characterisation and timing model development.
• Strong knowledge of LVF, AOCV, POCV, SOCV and related variation-aware timing methodologies.
• Experience correlating timing sign-off tools against SPICE simulation.
• Strong understanding of timing, noise, Monte Carlo and process variation analysis.
• Experience with EDA/CAD tools used within ASIC timing and physical design flows.
• Experience automating engineering workflows using Python, Perl, TCL and/or Bash.
• Working knowledge of SPICE extraction, modelling and aging/reliability methodologies.
• Understanding of advanced semiconductor technology nodes and modern physical design practices.
• Strong knowledge of STA and timing sign-off.

Preferred Qualifications

• Master's degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science or a related discipline.
• 3+ years of relevant ASIC, semiconductor design, verification, validation, integration or timing experience.
• 2+ years' experience working with architecture, ASIC or EDA design tools.
• 2+ years' experience with scripting/programming languages.
• Experience with design verification and semiconductor implementation methodologies.