Senior Staff Verification Engineer | Cork | Hybrid | Permanent

Reperio Human Capital Ltd; Munster; Hybrid; EUR 110,000 - 140,000; Full time

Job summary

Reperio Human Capital Ltd in Cork is assisting a global semiconductor manufacturer in recruiting a Senior Staff Verification Engineer to join their mixed-signal IC team in Cork and operate in a hybrid, permanent capacity.

You will own verification from test planning to final sign-off, build and maintain UVM testbenches and regression suites, and collaborate closely with analog and digital design teams to catch issues early in the design cycle.

Qualifications

• Strong, senior-level verification experience.
• Hands-on UVM and SystemVerilog.
• Mixed-signal verification experience.

Responsibilities

• Own verification of mixed-signal ICs, from test planning through to final sign-off.
• Build and maintain UVM testbenches, coverage models and regression suites.
• Work closely with the analog and digital design teams to catch issues early in the design cycle.
• Track coverage and drive closure against the verification plan.
• Help shape the team's verification approach and support other engineers.

Skills

Senior-level verification experience

UVM

SystemVerilog

Tools

UVM

SystemVerilog

Mixed-signal modelling

Job description

Senior Staff Verification Engineer | Cork | Hybrid | Permanent

Our client, a global semiconductor manufacturer, is looking for a Senior Staff Verification Engineer to join their mixed-signal IC team in Cork and play a key part in getting new products to market.

Responsibilities

• Own verification of mixed-signal ICs, from test planning through to final sign-off
• Build and maintain UVM testbenches, coverage models and regression suites
• Work closely with the analog and digital design teams to catch issues early in the design cycle
• Track coverage and drive closure against the verification plan
• Help shape the team's verification approach and support other engineers

Requirements

• Strong, senior-level design verification experience
• Hands-on UVM and SystemVerilog
• Mixed-signal verification experience
• A proactive, hands-on approach and a willingness to take ownership of your work

Nice to Have

• Analog/mixed-signal modelling (e.g. real-number modelling, Verilog-AMS)
• Experience guiding or leading verification work on a team