Verification Team Lead | Cork | Hybrid | Permanent

Reperio Human Capital Ltd; Munster; Hybrid; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Healthcare

Hybrid work

Competitive salary

RSUs

Job summary

Reperio Human Capital Ltd is hiring a Verification Team Lead in Cork for a global power semiconductor company. The role combines hands-on verification of mixed-signal power ICs with team leadership, mentoring and strategic development of the verification function.

You will architect UVM and SystemVerilog environments, drive coverage and sign-off criteria, and collaborate with design, firmware and test teams. On-site three days a week with hybrid working and a competitive package.

Qualifications

• Extensive verification experience with leadership responsibilities.
• Strong UVM and SystemVerilog skills.
• Experience in mixed-signal or AMS verification.
• Coverage-driven verification, SVA and regression management.
• Scripting in Python or Perl.

Responsibilities

• Lead, mentor and develop a team of verification engineers.
• Define verification strategy, methodology and sign-off criteria.
• Architect UVM/SystemVerilog environments at block, subsystem and SoC level.
• Verify analog, digital and firmware functions on mixed-signal power ICs.
• Own verification plans, regressions and coverage closure.
• Collaborate with design, firmware, applications and test teams.

Skills

UVM

SystemVerilog

AMS verification

Python

Perl

Leadership

Tools

Cadence vManager

Cadence vPlans

Job description

Verification Team Lead | Cork | Hybrid | Permanent

Our client, a global power semiconductor company, is seeking a Verification Team Lead to lead and grow their verification team while staying hands-on with mixed-signal power ICs.

Responsibilities

• Lead, mentor and develop a team of verification engineers.
• Define verification strategy, methodology and sign-off criteria.
• Architect UVM/SystemVerilog environments at block, subsystem and SoC level.
• Verify analog, digital and firmware functions on mixed-signal power ICs.
• Own verification plans, regressions and coverage closure.
• Work closely with design, firmware, applications and test teams.

Requirements

• Extensive design verification experience, including technical leadership or team lead responsibility.
• Strong UVM and SystemVerilog skills, including building verification environments.
• Mixed-signal or AMS verification experience.
• Coverage-driven verification, SVA and regression management.
• Scripting in Python, Perl or similar.
• Based in or around Cork, with three days a week on site.

Nice to Have

• Power IC, PMIC or power management experience.
• Cadence vManager, vPlans or real number modelling (SV-RNM).
• Protocol experience such as PMBus, SVID or I2C.

Benefits

• Competitive salary, RSUs, matching pension, Healthcare and hybrid working.