Senior Principal Analog IP Architect - Power & Clock

onsemi; Cork; Hybrid; EUR 120,000 - 160,000; Full time

Job summary

onsemi is seeking a Sr Principal Analog Design Engineer to lead analog IP design for the Treo platform in Cork, coordinating power, clock, and safety-related blocks within a digital-on-top SoC integration flow.

You will mentor engineers, own IP from concept to tape-out, ensure automotive-grade quality per ISO 26262, and collaborate with digital, verification, and layout teams to deliver robust, production-ready silicon.

Qualifications

• 12+ years hands-on analog design experience in IC or SoC development.
• Proven production IP design experience in power or clock blocks.
• Experience delivering automotive-grade analog IP with safety considerations.
• Ability to work in a digital-on-top integration flow and cross-disciplinary teams.

Responsibilities

• Architect and deliver analog IP blocks for power management, clocking, and error monitoring.
• Drive designs from concept through schematic, simulation, layout, and silicon validation.
• Own blocks from tape-out to volume production with reliability targets.
• Review designs and documentation to ensure quality and sign-off readiness.
• Collaborate with digital, verification, physical design, and systems teams.
• Apply ISO 26262 at the IP level and contribute to safety diagnostics and fault handling.
• Mentor junior engineers and lead design reviews.

Skills

Analog IP design

Power management IP

Clock IP design

Digital-on-top integration

Automotive-grade IP design

Mentorship & leadership

Education

Master's degree in Electrical Engineering or related field

Tools

Schematic capture tools

SPICE simulation

Layout collaboration tools

Job description

onsemi is seeking a Sr Principal Analog Design Engineer to lead analog IP design for the Treo platform in Cork, coordinating power, clock, and safety-related blocks within a digital-on-top SoC integration flow.

You will mentor engineers, own IP from concept to tape-out, ensure automotive-grade quality per ISO 26262, and collaborate with digital, verification, and layout teams to deliver robust, production-ready silicon.