Senior Lead Analog Layout Engineer - SERDES/UCIe

Cadence; Cork; On-site; EUR 90,000 - 140,000; Full time

Job summary

Cadence in Cork seeks a Sr Principal Engineer to lead the analog layout design for SERDES/UCIe products, collaborating with global teams on back-end flow from floor planning to sign-off. You will drive high-speed layout quality on leading-edge technology nodes and contribute to IP that spans chips to systems.

The role requires 7+ years in CMOS SERDES or high-speed I/O layout, proficiency with Cadence tools, and a proven track record delivering IP across time zones.

Qualifications

• Minimum 7 years in CMOS SERDES or high-speed I/O layout design.
• Proficient in SERDES blocks: driver, receiver, serializer/deserializer, clocking.
• Experience with high accuracy cells and IP blocks across global teams.
• BEng, MEng or PhD and strong communication skills.

Responsibilities

• Lead/back-end layout design for SERDES IP, from floor planning to sign-off.
• Design high-speed analog/mixed-signal blocks with foundry rules.
• Collaborate with circuit designers and global Cadence teams across time zones.
• Provide technical leadership in layout from block to PHY level.
• Mentor junior engineers and ensure timely, high-quality IP delivery.

Skills

CMOS SERDES

High-speed I/O

Analog layout

Team collaboration

Problem solving

Education

BEng/MEng/PhD

Tools

Cadence

Virtuoso

PVS

Job description

Cadence in Cork seeks a Sr Principal Engineer to lead the analog layout design for SERDES/UCIe products, collaborating with global teams on back-end flow from floor planning to sign-off. You will drive high-speed layout quality on leading-edge technology nodes and contribute to IP that spans chips to systems.

The role requires 7+ years in CMOS SERDES or high-speed I/O layout, proficiency with Cadence tools, and a proven track record delivering IP across time zones.