Senior Physical Design Engineer – Cork, Ireland

QUALCOMM, Inc.; Cork; On-site; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Salary bonus

Maternity/Paternity Leave

Employee stock purchase scheme

Matching pension scheme

Education Assistance

Relocation support

Life, Medical and Travel Insurance

Well-being subsidies

Job summary

QT Technologies Ireland Limited, part of Qualcomm's Dtech team in Cork, seeks a senior PD engineer to lead physical design of critical blocks on testchips and deliver digital sensor IP for SOCs. You will mentor a team of PD engineers and collaborate across sites.

Experience with PNR/STA at advanced nodes, and proficiency in Innovus, PrimeTime, Calibre, Redhawk, and Virtuoso is required. Degree in engineering with 7+ years' ASIC experience is expected.

Qualifications

• BE/B.Tech/M.Tech or equivalent with minimum 7 years of industry experience.
• Experience with PNR, STA and physical verification on advanced technology nodes.
• Good understanding of Physical design fundamentals and custom circuit design.
• Understanding of SPICE simulation with industry-standard simulators.
• Hands-on experience of EDA tools such as Innovus, PrimeTime, Calibre, Redhawk, Virtuoso.
• Basic knowledge of Formal Verification, CLP/LEC verifications at block level.
• Expertise in scripting languages like TCL/Python/Perl/SKILL.

Responsibilities

• Lead physical design of critical blocks on testchip.
• Deliver digital sensor IP to SOCs from mobile and compute domains.
• Cross-function/site collaboration and mentoring a team of PD engineers.

Skills

ASIC design

Physical design

Scripting languages

EDA tools scripting

Education

Bachelor’s degree in Science or Engineering

Master’s degree in Science or Engineering

PhD in Science or Engineering

Tools

Innovus

PrimeTime

Calibre

Redhawk

Virtuoso

Job description

QT Technologies Ireland Limited, part of Qualcomm's Dtech team in Cork, seeks a senior PD engineer to lead physical design of critical blocks on testchips and deliver digital sensor IP for SOCs. You will mentor a team of PD engineers and collaborate across sites.

Experience with PNR/STA at advanced nodes, and proficiency in Innovus, PrimeTime, Calibre, Redhawk, and Virtuoso is required. Degree in engineering with 7+ years' ASIC experience is expected.