Senior Analog/Mixed-Signal DDR IP Designer

QUALCOMM, Inc.; Ireland; On-site; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Salary, stock and performance related

Relocation and immigration support

Life, Medical, Travel Insurance

Employee stock purchase scheme

Education Assistance

Job summary

QT Technologies Ireland Limited, part of Qualcomm's design team, is seeking experienced analog/mixed-signal designers to work on Rx/Tx IO blocks, DLL, clocking and high-frequency circuits for DDR and chip-to-chip PHY IP.

You will contribute to architecture analyses for 2nm and beyond, focusing on low-power, high-speed designs across Snapdragon SoCs, with collaboration across mask layout and physical design teams in Cork.

Qualifications

• Master’s or Ph.D. in Science, Engineering, or related field.
• 3+ years ASIC design, verification, or related work experience.
• Experience with high-speed analog/mixed-signal circuits and LPDDR/IO blocks.

Responsibilities

• Architect and design high-speed mixed-signal circuits for LPDDR5/LPDDR6 and future systems.
• Develop custom blocks: Rx/Tx, clock distribution, DLL/PLL, references and band-gap cells.
• Circuit design for chip-to-chip architectures and pre-silicon validation.
• Schematic capture, SPICE analysis and post-silicon bring-up support.
• Collaborate with layout and physical design teams for IP delivery.
• Ensure signal integrity and power integrity in high-speed designs.

Skills

Analog mixed-signal design

High-speed DDR/SerDes/PLL

SPICE simulators

Schematic capture

Layout awareness

Communication skills

Scripting / GenAI

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

SPICE tools

Schematic capture tools

Job description

QT Technologies Ireland Limited, part of Qualcomm's design team, is seeking experienced analog/mixed-signal designers to work on Rx/Tx IO blocks, DLL, clocking and high-frequency circuits for DDR and chip-to-chip PHY IP.

You will contribute to architecture analyses for 2nm and beyond, focusing on low-power, high-speed designs across Snapdragon SoCs, with collaboration across mask layout and physical design teams in Cork.