Senior Design IP Architect & RTL Lead

Cadence Design Systems; Cork; Hybrid; EUR 120,000 - 180,000; Full time

Job summary

Cadence Design Systems in Cork, Ireland seeks a Design Engineering Architect to lead the development of key IP blocks and define architecture for UCIe, Ethernet, HBM, and PCIe. Based in Cork, you will drive RTL sign-off and collaborate with system architects, managers and software teams to ensure on-time, high-quality delivery.

You will mentor engineers, contribute to IP quality processes, and participate in industry standards bodies and conferences to reinforce Cadence’s leadership in

Qualifications

• Degree in Electrical/Electronic Engineering, microelectronics, or a related discipline.
• 15-20 years’ experience in microelectronics industry.
• Expert in Verilog/System Verilog RTL design essential.
• Expert in front-end design tools covering LINT, synthesis, CDC/RDC analysis essential.
• Experience of SoC architecture and development essential.
• Experience of technical team leadership essential.
• Excellent oral and written English essential.
• Self-motivated with excellent planning, interpersonal and with the ability to communicate complex concepts clearly and thoroughly.

Responsibilities

• Technical leadership of complex IP such as UCIe, Ethernet, HBM, and PCIe.
• Collaborate with system architects and product managers to define the architecture and specifications on standards such as UCIe, considering factors such as data rate, power consumption, and compatibility with industry standards.
• Hands-on leadership of RTL development from micro-architecture definition to IP sign-off for general release.
• Contribute to planning of activities and milestones for the digital development teams.
• Leadership of cross-functional technical meetings with Analog & Software counterparts.
• Support customer pre-sales and post-sales meetings.
• Develop, maintain and improve upon processes and procedures for efficient product execution, IP quality and industry best practices.
• Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001.
• Represent Cadence in Standards Body Working Groups e.g. IEEE, PCI-SIG, JEDEC, UCIe.
• Represent Cadence by presenting at Industry Conference such as IEEE, DAC.

Skills

Verilog/SystemVerilog RTL design

Front-end design tools

SoC architecture

Technical leadership

English communication

Education

Electrical/Electronic Engineering degree

Tools

LINT

Synthesis

CDC/RDC analysis

AXI/CHi-C2C

Job description

Cadence Design Systems in Cork, Ireland seeks a Design Engineering Architect to lead the development of key IP blocks and define architecture for UCIe, Ethernet, HBM, and PCIe. Based in Cork, you will drive RTL sign-off and collaborate with system architects, managers and software teams to ensure on-time, high-quality delivery.

You will mentor engineers, contribute to IP quality processes, and participate in industry standards bodies and conferences to reinforce Cadence’s leadership in