Senior Digital Verification Engineer – SystemVerilog/UVM

onsemi; Cork; On-site; EUR 75,000 - 95,000; Full time

Job summary

onsemi is seeking a highly motivated Staff Digital Verification Engineer to join our team working on the TREO platform focused on the verification of digital top-level subsystem IP for next-generation automotive and intelligent power applications.

The ideal candidate will have strong expertise in advanced verification methodologies, a solid understanding of digital design fundamentals, and demonstrated collaborative experience with analog and mixed-signal teams. A Bachelor's or Master's degree in Electronic Engineering is required along with 5+ years of industry experience in digital verification.

Qualifications

• 5+ years of industry experience in digital verification.
• Hands-on experience in SystemVerilog and UVM.
• Experience with constrained random verification methodologies.

Responsibilities

• Verify digital top-level subsystem IP within the TREO platform.
• Develop and execute constrained random verification environments.
• Collaborate closely with Digital design and mixed-signal teams.

Skills

SystemVerilog

UVM

Constrained random verification methodologies

Digital design fundamentals

Automotive semiconductor products

Debug automation

Education

Bachelor’s or Master’s degree in Electronic Engineering

Tools

Questa

Python

Job description

onsemi is seeking a highly motivated Staff Digital Verification Engineer to join our team working on the TREO platform focused on the verification of digital top-level subsystem IP for next-generation automotive and intelligent power applications.

The ideal candidate will have strong expertise in advanced verification methodologies, a solid understanding of digital design fundamentals, and demonstrated collaborative experience with analog and mixed-signal teams. A Bachelor's or Master's degree in Electronic Engineering is required along with 5+ years of industry experience in digital verification.