Senior Digital Design Engineer IP & Power Management

onsemi; Cork; On-site; EUR 90,000 - 120,000; Full time

Job summary

onsemi in Cork, Ireland seeks a Staff Digital Design Engineer to advance digital controllers for the Treo platform. You will work at the intersection of digital logic, analog control, and system-level IP, shaping platform-wide IP and collaborating with analog, verification, and back-end teams.

You will design and implement FSM-based controllers, deliver reusable RTL, and contribute to verification and back-end flows, while mentoring junior engineers and exploring AI-assisted design approaches.

Qualifications

• 5+ years of relevant experience in digital IC design.
• Strong hands-on experience with digital RTL design, including FSM-based control logic.
• Proven experience designing digital logic interfacing with analog power/clocking systems.
• Solid understanding of clock-domain crossing, reset strategies, low-power techniques, and timing constraints.

Responsibilities

• Architect, design, and implement digital FSM-based controllers for analog power/clocking blocks.
• Deliver robust digital-on-top subsystem IP for the Treo platform.
• Develop clean, maintainable RTL (SystemVerilog/Verilog) for reuse and scalability.
• Collaborate with analog/mixed-signal, verification, and physical design teams to meet timing, power, and area goals.
• Contribute to digital verification activities including testbench development and debugging.
• Support back-end flows, including synthesis, timing closure, and low-power considerations.
• Mentor junior engineers and promote best practices within Core Platform IP team.

Skills

RTL design

FSM-based control logic

Digital verification

CDC

Low-power techniques

Communication

Cross-functional collaboration

Tools

SystemVerilog

Verilog

Synthesis tools

STA

UVM

Job description

onsemi in Cork, Ireland seeks a Staff Digital Design Engineer to advance digital controllers for the Treo platform. You will work at the intersection of digital logic, analog control, and system-level IP, shaping platform-wide IP and collaborating with analog, verification, and back-end teams.

You will design and implement FSM-based controllers, deliver reusable RTL, and contribute to verification and back-end flows, while mentoring junior engineers and exploring AI-assisted design approaches.