Design Verification Engineer – DDR/UVM & Formal

AMD; Dublin; On-site; EUR 45,000 - 65,000; Full time

Benefits offered by this job

Benefits at a glance

Job summary

AMD Ireland is seeking a Graduate - Design Verification Engineer to verify DDR subsystems, writing SystemVerilog/UVM testbenches and formal properties. You will work with RTL engineers to refine clock gating and verification coverage, gaining broad exposure to advanced verification techniques.

The role emphasizes collaboration, strong problem-solving, and a learning path from a launch pad into senior verification roles within a dynamic hardware team.

Qualifications

• Bachelor's or Master's in Electronics/Computer/Electrical Engineering
• Experience or internship in design concepts or RTL verification
• Familiarity with Verilog/SystemVerilog
• Strong communication and teamwork skills

Responsibilities

• Drive verification for a design and write formal properties and assertions
• Coordinate with RTL engineers to implement logic design and verify clock gating
• Write tests, sequences, and testbench components in SystemVerilog and UVM, including Formal methods
• Achieve verification quality metrics like pass rates, code coverage and functional coverage

Skills

Digital design

Verification

Communication skills

Analytical thinking

Education

Electronics/Computer/Electrical Eng. degree

Tools

SystemVerilog

UVM

Formal verification

Job description

AMD Ireland is seeking a Graduate - Design Verification Engineer to verify DDR subsystems, writing SystemVerilog/UVM testbenches and formal properties. You will work with RTL engineers to refine clock gating and verification coverage, gaining broad exposure to advanced verification techniques.

The role emphasizes collaboration, strong problem-solving, and a learning path from a launch pad into senior verification roles within a dynamic hardware team.