Mixed-Signal Verification Engineer (SerDes/DDR/PLL)

QUALCOMM, Inc.; Ballyerra; On-site; EUR 70,000 - 100,000; Full time

Benefits offered by this job

Salary bonus

Maternity/Paternity Leave

Employee stock purchase scheme

Pension matching

Job summary

QUALCOMM Cork is seeking Mixed-Signal Design Verification Engineers to verify SerDes, DDR and PLL IP as part of the MSIP group. Work with analog and digital teams across architecture, design and software to integrate IP into Snapdragon products in 3nm and below nodes.

You will perform SV/UVM based verification, develop test benches, and drive pre/post-silicon validation with cross-functional teams in Cork, Ireland. Excellent communication and collaboration are essential.

Qualifications

• Bachelor's degree in Science, Engineering or related field.
• 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Experience in SV/UVM verification and test benches development.
• Knowledge of low power verification using UPF.
• Experience with Power Aware GLS verification flow and post-silicon validation.

Responsibilities

• SV/UVM based Design Verification of SerDes, DDR & PLL Mixed-Signal PHY IP.
• Develop and maintain unit/SoC/IP level test benches with constrained random verification.
• Collaborate with analog/digital teams to verify RTL and analog/mixed-signal designs.
• Support pre- and post-silicon verification and bench characterization.

Skills

SV/UVM verification

SystemVerilog

UVM

Constrained random verification

Low power verification

UPF

GLS verification

Test benches

Python scripting

Education

Bachelor's degree in Engineering, Computer Science or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

Verilog

SystemVerilog

UVM

Python

TCL

Perl

Shell scripting

Job description

QUALCOMM Cork is seeking Mixed-Signal Design Verification Engineers to verify SerDes, DDR and PLL IP as part of the MSIP group. Work with analog and digital teams across architecture, design and software to integrate IP into Snapdragon products in 3nm and below nodes.

You will perform SV/UVM based verification, develop test benches, and drive pre/post-silicon validation with cross-functional teams in Cork, Ireland. Excellent communication and collaboration are essential.