Microcontroller Subsystem Verification Engineer – ASIC / UVM / SystemVerilog / Formal Verification / ARM / RISC-V

European Tech Recruit; Cork; On-site; EUR 70,000 - 110,000; Full time

Job summary

European Tech Recruit is seeking a Staff Microcontroller Subsystem Verification Engineer to design and implement verification environments for complex processor and microcontroller subsystems. You will work in a highly collaborative, multicultural engineering environment to advance next-generation digital and embedded processing technologies.

Key requirements include UVM-based verification, SystemVerilog, formal verification, and experience with ARM and/or RISC-V ISA verification, plus RTL

Qualifications

• 3+ years of professional ASIC design verification experience.
• Strong experience with UVM-based verification methodologies.
• Strong experience with SystemVerilog and verification testbench development.
• Experience with constrained‑random and coverage‑driven verification.
• Familiarity with ARM and/or RISC-V instruction set architecture verification.
• Strong experience using RTL simulation tools.

Responsibilities

• Develop and deploy industry-standard verification methodologies including UVM and formal verification.
• Create and maintain comprehensive verification testbenches and reusable verification components.
• Develop UVCs, C models, and reusable vertical and horizontal verification environments.
• Develop constrained‑random and coverage‑driven verification environments.
• Perform functional, code, and line coverage analysis and address coverage gaps with design teams.
• Collaborate with RTL design, SoC, validation, and system engineering teams to resolve verification issues.

Skills

UVM-based verification

SystemVerilog

Formal verification

Constrained-random verification

Coverage-driven verification

Testbench development

RTL verification collaboration

Education

Bachelor's degree in Science/Engineering/EE/CE

Tools

RTL simulators

C models

Job description

Microcontroller Subsystem Verification Engineer – ASIC / UVM / SystemVerilog / Formal Verification / ARM / RISC-V

We are currently partnered with a global technology organisation developing advanced semiconductor and system‑on‑chip solutions across multiple technology markets. Their Microcontroller Subsystem IP team plays a key role in enabling embedded processing solutions, working across areas including security, power management, and other SoC functions.

As part of their continued development of next‑generation digital and embedded processing technologies, they are looking to hire a Staff Microcontroller Subsystem Verification Engineer to develop and implement verification environments for complex processor and microcontroller subsystems within a highly collaborative, multicultural engineering environment.

Key responsibilities

• Develop and deploy industry-standard verification methodologies including Universal Verification Methodology (UVM) and formal verification
• Create and maintain comprehensive verification testbenches and reusable verification components
• Develop Universal Verification Components (UVCs), C models, and reusable vertical and horizontal verification environments
• Develop constrained‑random and coverage‑driven verification environments
• Perform functional, code, and line coverage analysis and work with design teams to address coverage gaps
• Collaborate closely with RTL design, SoC, validation, and system engineering teams to identify and resolve verification issues

Key requirements

• Bachelor's degree in Science, Engineering, Computer Engineering, Electrical Engineering, or a related technical discipline
• 3+ years of professional ASIC design verification experience
• Strong experience with UVM-based verification methodologies
• Strong experience with SystemVerilog and verification testbench development
• Experience with constrained‑random and coverage‑driven verification
• Familiarity with ARM and/or RISC-V instruction set architecture verification
• Strong experience using RTL simulation tools

Keywords

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