Lead Physical Design Engineer: RTL-to-GDSII Champion

1020 ADBV Ireland; Limerick; On-site; EUR 120,000 - 180,000; Full time

Job summary

Analog Devices, Inc. is seeking a Principal Physical Design Engineer in Ireland to lead end-to-end RTL-to-GDSII implementation for complex SoCs. You will manage floorplanning, timing closure, routing, and signoff with CAD/EDA tools, guiding a distributed team and coordinating with design, DFT, verification, and CAD groups.

The role requires a senior track record in physical design, strong leadership, and a deep understanding of timing, reliability, and quality targets across technology nodes.

Qualifications

• 10+ years of physical design experience with tape-outs on advanced nodes.
• Hands-on experience with industry-standard physical design flows.

Responsibilities

• Own RTL-to-GDSII implementation, including floorplanning, CTS, routing, equivalence checking, ECO implementation, and STA closure.
• Apply a strong working knowledge of SDC timing constraints and timing closure to review results and feedback.
• Drive implementation flows using Cadence and/or Synopsys, including flow debugging and signoff activities.
• Lead setup and hold timing closure, IR/EM analysis, congestion resolution, and physical verification.
• Lead signoff activities, including multi-mode/multi-corner STA, DRC/LVS, and power analysis.
• Provide leadership for a geographically distributed Physical Design team and manage priorities and milestones.

Skills

Physical design leadership

RTL-to-GDSII expertise

Timing closure expertise

Education

B.Tech./M.Tech. in Electrical or Electronics Engineering

Tools

Cadence

Synopsys

Job description

Analog Devices, Inc. is seeking a Principal Physical Design Engineer in Ireland to lead end-to-end RTL-to-GDSII implementation for complex SoCs. You will manage floorplanning, timing closure, routing, and signoff with CAD/EDA tools, guiding a distributed team and coordinating with design, DFT, verification, and CAD groups.

The role requires a senior track record in physical design, strong leadership, and a deep understanding of timing, reliability, and quality targets across technology nodes.