SoC Validation/FPGA Engineer (Senior Engineer II)

Microchip Technology Inc.; Dublin; On-site; EUR 65,000 - 85,000; Full time

Benefits offered by this job

Leadership Passage Programs

Opportunities for career growth

Commitment to employee development

Job summary

Microchip Technology Inc. is seeking a skilled professional to drive the architecture and design of high-speed SoC subsystems. This role demands strong embedded software design experience and the ability to collaborate with various teams to deliver production-ready SoC features.

The ideal candidate will have a background in SoC architecture and embedded software, with excellent communication skills and a commitment to quality. Join us to contribute to technology that powers the world!

Qualifications

• 7+ years experience in SoC architecture or 6+ years with a master's
• In-depth knowledge of FPGA/SoC architectures and system-level IC design
• Experience with board-level debug using oscilloscopes and logic analyzers
• Strong background in silicon validation and failure analysis

Responsibilities

• Drive architecture and design of high-speed SoC subsystems
• Collaborate with teams to develop and review RTL/design implementations
• Lead block- and system-level bring-up and debug
• Own documentation and design reviews for production-ready SoC features

Skills

SoC architecture

Embedded software design

RTL coding in Verilog/VHDL

Debugging skills with various tools

Communication skills

Education

BS EE / CE or MS EE / CE

Tools

ModelSim

Synthesis tools (Synplicity)

FPGA tools

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi‑billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally‑recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values‑based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Job Description

Drive architecture and design of high‑speed SoC subsystems and interfaces from concept through integration. Define micro‑architecture, write clear specifications, and collaborate with RTL, verification, firmware, and physical design teams. Develop and review RTL/design implementations for performance, power, area, and testability trade‑offs. Lead block‑ and system‑level bring‑up, debug, and root‑cause analysis across simulation, emulation, and silicon. Own documentation, design reviews, and cross‑functional execution to deliver robust, production‑ready SoC features. Experience in developing complex bare‑metal firmware mainly in C (but also assembly) on ARM Cortex‑M and RISC‑V processors. Good understanding of embedded firmware/software development process. Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming. Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, Watchdog, Timer, UART, Ethernet, PCIe and USB. Design knowledge with RTL coding in Verilog / VHDL. Experience in using FPGA tool flow. Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools. Strong commitment to quality and customer satisfaction. Excellent verbal and written communication skills in English. Mentor junior validation engineers. Able to travel 0‑2 times annually if required. Must be willing to work outside of normal business hours to match timing with India Standard Time as well as Pacific Standard time. Must be adept with using AI tools to automate design builds and processes.

Requirements / Qualifications

Minimum qualifications

• BS EE / CE with 7+ years OR MS EE/CE with 6+ years, and experience in SoC architecture, embedded software design and debug
• In‑depth knowledge of FPGA/SoC architectures, hardware architectures, system‑level IC design, and end‑use scenario creation
• Validation & Debug: Strong background in SoC prototype emulation, silicon validation, failure analysis, and debug
• Lab skills: Board‑level debug on PCBs (digital logic & analog circuits) using oscilloscopes, logic analyzers, protocol analyzers/exercisers, integrated logic analyzers (Synopsys Identify, Xilinx ChipScope, Altera SignalTap or Lattice Reveal)
• Debug tools: CPU debug (SoftConsole, EWARM, Keil); Trace debug (Lauterbach, Ultradevelop)
• C/C++, assembly; bare‑metal firmware on ARM Cortex‑M and RISC‑V; diagnostic code (bare‑metal, Zephyr, RTOS, embedded Linux)
• Standards & Peripherals: JTAG, SVF, IEEE 1532, STAPL; validation of SPI, I2C, UART, Ethernet, PCIe, USB
• RTL & EDA: Verilog/VHDL coding; Simulation (ModelSim), Synthesis (Synplicity)
• Soft skills: Strong communication (English), quality commitment

Preferred qualifications

• Coding standards & static analysis; Atlassian (Confluence, JIRA), Bitbucket, Git; Perl/TCL scripting
• Emerging Tech: Agentic AI for embedded software development and peripheral driver debug (e.g. Claude Code, ChipAgents, GitHub Co‑pilot)
• High‑Speed SERDES: Bring‑up and debug of 32Gbps PCS/PMA controllers
• Serial protocols (PHY through transaction layers):
  • Aurora, Ethernet (1G–400G, SGMII/XGMII variants), USB 3.0
  • SERDES controllers: PCIe Gen3/4/5, Interlaken, OTN/SONET/SDH, xPON, JESD204C
  • SDI (SD/HD/3G/12G), DisplayPort, HDMI
  • CPRI, Serial RapidIO, SATA, Fiber Channel, CoaXpress, HMC, Firewire

Percentage of time spent

Documentation – 20%, Design creation & verification – 30%, Lab bring‑up & debug – 50%.

Essential physical functions and working conditions

50% work in front of computer, 50% work in the lab.

Travel time

0% – 25%.