Staff Design Engineer

Arm Limited; United Kingdom; On-site; GBP 110,000 - 160,000; Full time

Job summary

Arm Limited is seeking an experienced Staff Subsystem Design Engineer to lead RTL design and integration of complex IP and subsystem solutions for next-generation Edge and Cloud AI platforms.

You will craft microarchitectures, refine system specifications, and collaborate across architecture, verification, and implementation teams to deliver high-quality designs that meet power, performance and area targets.

Qualifications

• Bachelor's/Master's/PhD in Electrical Engineering, Electronics Engineering, Computer Engineering or a related discipline.
• 10+ years of relevant industry experience.

Responsibilities

• Analyse architectural and system specifications and refine solutions with architects.
• Develop subsystem and IP microarchitecture specifications from high-level requirements.
• Design new IP and subsystem logic and integrate existing Arm and third-party IP.
• Understand IP functionality, interfaces and system interactions for robust integration.
• Develop and maintain design intent, including UPF and timing constraints where applicable.
• Perform and drive design quality checks including Lint, CDC, RDC, X-propagation and synthesis.
• Collaborate with verification teams to review test plans and support debugging.
• Work with implementation, performance and power teams to meet requirements.
• Improve design methodologies and flows for evolving subsystem and IP development.
• Plan and drive work to ensure high-quality, timely delivery.
• Provide technical guidance and design reviews as part of the team.

Skills

SystemVerilog

RTL design

IP/subsystem design

Microarchitecture

AMBA AXI

Synthesis

Power management

Computer architecture

Collaboration

Communication

Education

Bachelor's/Master's/PhD in Electrical/Electronics/ Computer Engineering

Tools

EDA tools

SVA/UVM

Cadence/Synopsys

Job description

StaffSubsystemDesign Engineer

Job Overview

Arm’s IP and Technology team inSolutions Engineeringdepartmentevelop subsystem solutions and SoC IPs for next-generation systems targeting Edge AI, PhysicalAIand Cloud AI. We work across Arm, bringing together the latest Arm technologies and selected third-party IP, as well as developing our own IP where needed, to deliver highly integrated and optimized solutions.

We are looking for an experienced,motivatedand creative Staff Subsystem Design Engineer with a strong background in RTL,IPdesignand subsystems. You will work on challenging subsystem designs, developing microarchitectures,designingand integrating IP, and solving complex engineering problems across power, performance,areaand implementation.

You will work with a diverse, global group of engineers and collaborate across architecture, verification,implementationand other technology teams to deliver high-quality designs.

Responsibilities

As a Staff Subsystem Design Engineer, you will be involved in the specification, microarchitecture, RTL design and integration of complex IPs and compute subsystems.

Your key responsibilities will include:

• Analyse architectural and system specifications, understand implementation challenges and collaborate with architects to refine solutions.
• Develop subsystem and IP microarchitecture specifications from high-level requirements.
• Design new IP and subsystem logic whererequired, as well as integrate existing Arm and third-party IP into complete subsystem solutions.
• Understand IP functionality,interfacesand system-level interactions to ensure robust integration within the subsystem.
• Develop andmaintaindesign intent, including UPF and timing constraints, where applicable.
• Perform and drive design quality checks including Lint, CDC, RDC, X-propagation,synthesisand other static design checks.
• Navigate architectural and implementation trade-offs and clearly articulate the rationale behind design decisions.
• Work closely with verification teams to review test plans, supportverificationand debug complex design issues.
• Collaborate with implementation,performanceand power teams to ensure designs meet functional, timing, area,powerand performance requirements.
• Improve design methodologies and flows to address evolving subsystem and IP development needs.
• Plan and drive your work to ensure high-quality andtimelydelivery.
• Providetechnical guidance, design reviews and support to other engineers while contributing effectively as part of the wider team.

Required Skills and Experience

In addition to holding a Bachelor's,Master'sor PhD degree in Electrical Engineering, Electronics Engineering, Computer Engineering or a related discipline, you will have 10+ years of relevant industry experience anddemonstrate:

• Extensive hands-on experience in digital RTL design and microarchitecture development usingSystemVerilogand/or Verilog.
• A strong delivery record of sophisticated IPorRTL subsystem designs.
• Deep understanding of RTL design techniques and methodologies for complex subsystem and SoC development.
• Ability to analyse high-level specifications and translate them into efficient and robust microarchitectures.
• Familiarity with industry-standard EDA tools and methodologies.
• Experience with static design checks including Lint, CDC, RDC and X-propagation.
• Experience with synthesis, timinganalysisand power-management techniques.
• Understanding of low-power design methodologies, including UPF, clock/power gating and multiple power domains.
• Ability to navigate performance, power, area,timingand complexity trade-offs and clearly articulate the rationale behind engineering decisions.
• Knowledge of on-chip protocols and interfaces including AMBA AXI,APBand streaming interfaces.
• Strong understanding of computer architecture and processor-based systems.
• Knowledge of AI-powered software development tools and scripting workflows, including AI coding assistants such as Codex, GitHub Copilot, or equivalent technologies.
• Excellent communication,collaborationand teamwork skills.
• A self-driven and motivated approach, with the ability to take ownership of complex technical problems and drive them to completion.

Nice to Have Skills and Experience

• Experience with Arm-based designs, Arm System Architectures and AMBA protocols.
• Experience with advanced low-power RTL design and power-aware verification, including power/clock gating, retentionand DVFS.
• Proficiencywith SystemVerilogAssertions (SVA) and formal verification techniques, and UVM.
• Knowledge of Functional Safety methodologies and safety-related hardware design.
• Experience developing or improving RTL, IP and subsystem design flows and methodologies.
• High-level programming experience such as C/C++.

In Return

You will have the opportunity to apply your engineering experience to challenging subsystem and IP design problems, working with teams across Arm to develop technologies for the next generation of AI systems.

You will be part of a diverse global engineering organization where you can develop new IP & influence subsystems microarchitecture and create highly optimized designs, while helping advance the performance and power efficiency of futuresystem.

Our 10x Mindset

At Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset

Use of AI in Your Application

At Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application, and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact [e-mail] so we can support you.

Recruitment Adjustments and Accommodations

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed to the extent necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.