STA Engineer – Drive Full-Chip Timing for ASIC/SoC

IC Resources; Cambridge; On-site; GBP 60,000 - 90,000; Full time

Job summary

IC Resources in Cambridge is seeking a STA Engineer to join a collaborative team delivering full-chip timing analysis across ASIC/SoC projects. The role covers design-to-silicon stages, with exposure to PPA trade-offs and sign-off readiness.

You will work with RTL, Physical Design and Verification to optimize timing, power and area, and you should bring strong scripting skills and industry-standard EDA tool experience.

Qualifications

• Strong academic background in Electronics or Electrical Engineering.
• Proven industry experience in Static Timing Analysis, Physical Design or ASIC implementation.
• Deep understanding of timing closure methodologies and sign-off flows for advanced ASIC/SoC designs.
• Strong scripting skills using Tcl, Perl or Python to automate timing analysis.

Responsibilities

• Perform full-chip and block-level static timing analysis on ASIC/SoC designs.
• Drive timing closure across all implementation stages from synthesis to sign-off.
• Analyse and resolve setup, hold, clock gating and SI issues.
• Develop timing constraints and ensure accurate timing models and methodologies.
• Collaborate with Physical Design, RTL Design and Verification to optimise PPA.
• Support sign-off activities including STA and silicon bring-up readiness.

Skills

Static Timing Analysis

Timing closure

Scripting (Tcl, Python, Perl)

Cross-functional teamwork

ASIC/SoC experience

Education

Electronics / Electrical Engineering degree

Tools

Synopsys PrimeTime

Design Compiler

Place-and-Route tools

Job description

IC Resources in Cambridge is seeking a STA Engineer to join a collaborative team delivering full-chip timing analysis across ASIC/SoC projects. The role covers design-to-silicon stages, with exposure to PPA trade-offs and sign-off readiness.

You will work with RTL, Physical Design and Verification to optimize timing, power and area, and you should bring strong scripting skills and industry-standard EDA tool experience.