Remote Senior Physical Design & STA Engineer (5nm ASICs)

Swediumglobal; Greater London; Hybrid; GBP 90,000 - 130,000; Full time

Job summary

Swedium Global Services is seeking a Senior Physical Design Engineer (remote from the UK/EU) to drive timing closure for ASIC/SoC designs across advanced nodes, including <5nm processes. You will work closely with PD, RTL, Synthesis, and Signoff teams to resolve timing and clock-related challenges.

The role requires 5+ years in Physical Design/STA, strong experience with Synopsys or Cadence tools, and hands-on knowledge of SDC, PVT corners, and timing ECOs. Remote work from the UK/EU is supported.

Qualifications

• 5+ years of experience in Physical Design / STA.
• Hands-on experience with Static Timing Analysis and timing closure.
• Experience on advanced technology nodes below 5nm (4nm/3nm).
• Strong experience with TSMC process technologies.
• Knowledge of setup/hold analysis, clock analysis, timing constraints, SDC, PVT corners, and timing ECOs.

Responsibilities

• Perform Static Timing Analysis (STA) for ASIC/SoC designs.
• Drive timing closure across multiple design stages and corners.
• Analyze/reslove setup and hold violations.
• Perform timing analysis across PVT corners and modes.
• Collaborate with PD, RTL, Synthesis, and Signoff teams to resolve timing issues.
• Review and debug timing constraints including SDC.
• Support timing signoff activities for advanced nodes (<=5nm).
• Analyze clock skew, transitions, capacitance, and fanout issues.
• Contribute to methodology development and automation for timing analysis.

Skills

Static Timing Analysis

Timing closure

Advanced nodes <5nm

TSMC process technologies

Clock tree analysis

Setup/hold analysis

SDC

Synopsys & Cadence EDA tools

Tools

Synopsys EDA tools

Cadence EDA tools

Job description

Swedium Global Services is seeking a Senior Physical Design Engineer (remote from the UK/EU) to drive timing closure for ASIC/SoC designs across advanced nodes, including <5nm processes. You will work closely with PD, RTL, Synthesis, and Signoff teams to resolve timing and clock-related challenges.

The role requires 5+ years in Physical Design/STA, strong experience with Synopsys or Cadence tools, and hands-on knowledge of SDC, PVT corners, and timing ECOs. Remote work from the UK/EU is supported.