STA Engineer

IC Resources; Cambridge; On-site; GBP 60,000 - 90,000; Full time

Job summary

IC Resources in Cambridge is seeking a STA Engineer to join a collaborative team delivering full-chip timing analysis across ASIC/SoC projects. The role covers design-to-silicon stages, with exposure to PPA trade-offs and sign-off readiness.

You will work with RTL, Physical Design and Verification to optimize timing, power and area, and you should bring strong scripting skills and industry-standard EDA tool experience.

Qualifications

• Strong academic background in Electronics or Electrical Engineering.
• Proven industry experience in Static Timing Analysis, Physical Design or ASIC implementation.
• Deep understanding of timing closure methodologies and sign-off flows for advanced ASIC/SoC designs.
• Strong scripting skills using Tcl, Perl or Python to automate timing analysis.

Responsibilities

• Perform full-chip and block-level static timing analysis on ASIC/SoC designs.
• Drive timing closure across all implementation stages from synthesis to sign-off.
• Analyse and resolve setup, hold, clock gating and SI issues.
• Develop timing constraints and ensure accurate timing models and methodologies.
• Collaborate with Physical Design, RTL Design and Verification to optimise PPA.
• Support sign-off activities including STA and silicon bring-up readiness.

Skills

Static Timing Analysis

Timing closure

Scripting (Tcl, Python, Perl)

Cross-functional teamwork

ASIC/SoC experience

Education

Electronics / Electrical Engineering degree

Tools

Synopsys PrimeTime

Design Compiler

Place-and-Route tools

Job description

Established technology company in Cambridge that develops high-volume computing and embedded products. They are hiring a STA Engineer to join its expanding team.

This is an excellent opportunity for a STA Engineer to work within a highly collaborative team, contributing across the full chip development lifecycle from early design stages through silicon delivery and product release. The team is relatively small, giving engineers broad exposure and the opportunity to have a genuine impact on product development.

Responsibilities

• Perform full-chip and block-level static timing analysis on complex ASIC and SoC designs
• Drive timing closure across all implementation stages, from synthesis through sign-off
• Analyse and resolve setup, hold, clock gating and signal integrity issues
• Develop timing constraints and ensure accurate timing models and methodologies are implemented
• Work closely with Physical Design, RTL Design and Verification teams to optimise performance, power and area (PPA)
• Support sign-off activities including STA, timing verification and silicon bring-up readiness
• Debug and resolve complex timing issues within advanced process nodes

Requirements

• A strong academic background in Electronics, Electrical Engineering or a related discipline
• Proven industry experience in Static Timing Analysis, Physical Design or ASIC implementation
• Deep understanding of timing closure methodologies and sign-off flows for advanced ASIC and SoC designs
• Strong knowledge of industry-standard EDA tools such as Synopsys PrimeTime, Design Compiler and place-and-route tools
• Experience working on complex, high-performance semiconductor products, ideally within AI, HPC or data centre applications
• Strong scripting skills using Tcl, Perl or Python to automate timing analysis and improve design methodologies
• Excellent communication skills and the ability to work effectively within cross-functional engineering teams

This is a fantastic opportunity to join a company with a strong engineering culture, work on technically challenging products and become part of a close-knit team where your contributions will have a direct impact.

For more information on this opportunity, or other Physical Design positions across the UK and Europe, please contact Jordan Browne.