DFT Engineer - Next-Gen ASIC & SoC Testing

IC Resources; Cambridge; On-site; GBP 60,000 - 95,000; Full time

Job summary

IC Resources is seeking a DFT Engineer for its Cambridge ASIC team delivering next‑generation silicon. You will define, implement and verify DFT methodologies across SoC designs from architecture through production, collaborating closely with Design, Verification, Physical Implementation and Product Engineering teams.

The role focuses on robust test infrastructures—scan, MBIST, EDT, SSN and IJTAG—plus timing constraints, power analysis and formal equivalence checking to ensure high-quality

Qualifications

• Experience with modern ASIC/SoC development flows.
• Strong knowledge of DFT methodologies and tools.
• Familiarity with test access standards (IJTAG) and low-power verification.

Responsibilities

• Define DFT strategies at chip, subsystem and IP level.
• Implement DFT methodologies across complex ASIC designs.
• Insert and integrate scan, MBIST, EDT, SSN and IJTAG-based test infrastructure.
• Verify DFT implementation and debug issues throughout the design cycle.
• Support timing, power analysis and formal equivalence checking.
• Collaborate with Physical Design and Verification teams.
• Mentor other engineers.

Skills

ASIC/SoC flow

Tcl scripting

Python scripting

Collaboration

Tools

Siemens Tessent DFT

IJTAG

UPF/low-power concepts

Job description

IC Resources is seeking a DFT Engineer for its Cambridge ASIC team delivering next‑generation silicon. You will define, implement and verify DFT methodologies across SoC designs from architecture through production, collaborating closely with Design, Verification, Physical Implementation and Product Engineering teams.

The role focuses on robust test infrastructures—scan, MBIST, EDT, SSN and IJTAG—plus timing constraints, power analysis and formal equivalence checking to ensure high-quality