Senior CPU Physical Design Engineer

IC Resources; Cambridge; On-site; GBP 70,000 - 110,000; Full time

Job summary

IC Resources is seeking an experienced Physical Design Engineer to join its team, delivering high-performance CPU IP on advanced process nodes. You will participate in the full physical design flow from synthesis to sign-off in Cambridge.

Collaborating with RTL, architecture, STA and methodology teams, you will optimize timing, power and area, drive floorplanning, power planning, CTS and routing, and develop automation using TCL, Python or Perl.

Qualifications

• Degree in Electrical/Electronic Engineering or related field.
• Strong hands-on experience in Physical Design for ASIC/CPU/SoC designs.
• Experience across full implementation flow including floorplanning, placement, CTS and sign-off.
• Familiarity with industry-standard EDA tools such as Innovus, ICC2, Fusion Compiler.

Responsibilities

• Drive the physical implementation of advanced CPU blocks from synthesis through to sign-off.
• Take ownership of key physical design activities including floorplanning, power planning, placement, clock tree synthesis, routing and physical verification.
• Work closely with RTL, architecture, STA and methodology teams to optimise designs for performance, power and area.
• Analyse and resolve timing, congestion, power and DRC/LVS issues throughout the implementation cycle.
• Develop and enhance automation, flows and methodologies using TCL, Python or Perl scripting.
• Support design closure across advanced process technologies and contribute to best practices for future projects.
• Collaborate with cross-functional teams to deliver high-quality silicon on aggressive project schedules.

Skills

Physical Design

ASIC/CPU design

Scripting (TCL)

Python

Perl

Education

Bachelor's degree in Electrical/Electronic Engineering or related

Tools

Innovus

ICC2

Fusion Compiler

Job description

IC Resources is seeking an experienced Physical Design Engineer to join its team, delivering high-performance CPU IP on advanced process nodes. You will participate in the full physical design flow from synthesis to sign-off in Cambridge.

Collaborating with RTL, architecture, STA and methodology teams, you will optimize timing, power and area, drive floorplanning, power planning, CTS and routing, and develop automation using TCL, Python or Perl.