SoC Verification Engineer — UVM, SystemVerilog, AI/Video

Amazon; Cambridge; On-site; GBP 70,000 - 100,000; Full time

Benefits offered by this job

Restaurant d'entreprise

Indemnités de stage/alternance

Job summary

Evi Technologies Limited is seeking a Design Verification Engineer to advance energy-efficient SoC designs for Amazon devices. You will contribute to verification strategies, test plans, and cross-functional collaboration, ensuring robust silicon for Ring and Blink products.

Applicants should have a strong background in UVM-based verification, SystemVerilog proficiency, and experience across block to system level verification.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• Experience with UVM-based testbench development.
• Experience in ASIC or SOC verification.
• Proven ability to develop test plans and verification infrastructure.
• Practical knowledge of verification methodologies from block to system level.
• Proficiency in SystemVerilog.
• Experience in identifying and resolving complex design and verification issues.

Responsibilities

• Develop and implement UVM-based verification environments.
• Create verification plans at block and system levels.
• Design and implement verification components including assertions, traffic generators, and scoreboards.
• Collaborate with cross-functional teams to evaluate design testability and verification requirements.
• Lead debug efforts and provide solutions for complex technical challenges.

Skills

UVM testbench development

SystemVerilog

ASIC/SoC verification

Test plans & verification infra

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Python

Perl

Formal verification tools

Job description

Evi Technologies Limited is seeking a Design Verification Engineer to advance energy-efficient SoC designs for Amazon devices. You will contribute to verification strategies, test plans, and cross-functional collaboration, ensuring robust silicon for Ring and Blink products.

Applicants should have a strong background in UVM-based verification, SystemVerilog proficiency, and experience across block to system level verification.