UK Design Verification Engineer — AI Hardware & IP Testbenches

IC Resources; Cambridge; On-site; GBP 108,000 - 132,000; Full time

Benefits offered by this job

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Performance-based bonus scheme

Job summary

A tech recruitment firm is seeking a Design Verification Engineer in Cambridge, UK. The role involves creating test plans, writing UVM/SystemVerilog code, and collaborating with teams. Candidates should have over 6 years in verification and a degree in a related field. A competitive salary of up to £120,000 is offered along with share options and bonuses.

Qualifications

• 6+ years of current hands-on experience in block-level/IP-level/SoC-level verification.
• Deep experience with UVM-based testbenches.
• Experience on working with IP's for caches, cache coherency, and memory subsystems is a plus.

Responsibilities

• Create test plans for highly configurable IPs.
• Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards.
• Collaborate with software teams to define and implement configurable testbenches.

Skills

Verilog

SystemVerilog

UVM-based testbenches

Knowledge of Arm AMBA protocols

Experience with formal verification techniques

Education

BS, MS in Electrical Engineering, Computer Engineering or Computer Science

Job description

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