SoC DV Engineer — UVM/SystemVerilog & Embedded C

DELTACLASS TECHNOLOGY SOLUTIONS LIMITED; West Bromwich; On-site; GBP 60,000 - 80,000; Full time

Job summary

DELTACLASS TECHNOLOGY SOLUTIONS LIMITED is seeking experienced SoC Design Verification Engineers to verify next-generation multi-die SoC designs. You will perform subsystem- and SoC-level functional verification using SystemVerilog/UVM, and develop processor-based C tests for embedded cores.

You will reuse and enhance existing UVM testbenches, debug complex RTL simulations, and drive regression and coverage closure with a disciplined verification plan and cross-functional collaboration.

Qualifications

• Experience verifying complex SoCs using SystemVerilog/UVM.
• Ability to develop processor-based C tests for embedded cores.

Responsibilities

• Verify subsystem- and SoC-level functionality for next-gen multi-die designs.
• Reuse and enhance existing UVM testbenches to drive verification.
• Debug RTL simulations and manage regression and coverage closure with a disciplined plan.

Skills

SystemVerilog/UVM

Embedded C test development

Tools

UVM testbenches

RTL debugging tools

Job description

DELTACLASS TECHNOLOGY SOLUTIONS LIMITED is seeking experienced SoC Design Verification Engineers to verify next-generation multi-die SoC designs. You will perform subsystem- and SoC-level functional verification using SystemVerilog/UVM, and develop processor-based C tests for embedded cores.

You will reuse and enhance existing UVM testbenches, debug complex RTL simulations, and drive regression and coverage closure with a disciplined verification plan and cross-functional collaboration.