Senior Verification Engineer — L1 IP (FPGA to ASIC)

Yoh, A Day & Zimmermann Company; Southampton; On-site; GBP 70,000 - 100,000; Full time

Job summary

Yoh, A Day & Zimmermann Company is seeking a Senior Verification Engineer to own UVM-based verification across complex communications IP, taking it from specification through to sign-off. You will work with architects, RTL designers and systems engineers to develop verification plans and build SystemVerilog/UVM environments.

You will create coverage models, debug issues across RTL and verification environments, and contribute from early spec through final sign-off as the project scales for

Qualifications

• Experience with SystemVerilog and UVM in verification.
• Background in ASIC and/or FPGA verification.
• Proficient in Linux scripting (Python, Tcl or Bash).

Responsibilities

• Own UVM-based verification across complex IP from specification to sign-off.
• Develop verification plans and test strategies.
• Build SystemVerilog/UVM environments and components.
• Create coverage models and debug RTL/verification issues.
• Collaborate with architects, RTL designers and systems engineers.

Skills

SystemVerilog

UVM

ASIC verification

FPGA verification

Coverage-driven verification

Assertion-based verification

Python

Tcl

Bash

Job description

Yoh, A Day & Zimmermann Company is seeking a Senior Verification Engineer to own UVM-based verification across complex communications IP, taking it from specification through to sign-off. You will work with architects, RTL designers and systems engineers to develop verification plans and build SystemVerilog/UVM environments.

You will create coverage models, debug issues across RTL and verification environments, and contribute from early spec through final sign-off as the project scales for