Senior Verification Engineer

AccelerComm Ltd; Cambridge; Hybrid; GBP 65,000 - 90,000; Full time

Benefits offered by this job

Bonus up to 20% of salary

EMI share options

Pension

Private health insurance

Flexible working hours

Hybrid working

Job summary

AccelerComm Ltd in Cambridge is seeking a Senior Verification Engineer to lead RTL verification of advanced wireless IP for ASIC and FPGA implementations. You will develop verification plans, build SystemVerilog/UVM environments and ensure coverage and quality before tape-out.

The role requires 3+ years in digital verification, strong SV/UVM, Linux scripting, and experience with coverage-driven methods. A hybrid work model in Cambridge is available with competitive compensation.

Qualifications

• Degree in Electronic Engineering, Computer Engineering or a related discipline.
• 3+ years experience verifying digital ASIC/FPGA designs.
• Strong SystemVerilog and UVM skills.
• Understanding of RTL design principles and hardware implementation.
• Experience with coverage-driven and assertion-based verification.
• Linux proficiency and scripting skills (Python, Tcl or Bash).
• Strong analytical, debugging and problem-solving skills.
• Experience using AI to accelerate verification without sacrificing quality.”
• Ability to work across multiple teams.

Responsibilities

• Develop verification plans from design and architecture specifications.
• Create and maintain SystemVerilog/UVM verification environments.
• Develop testbenches, assertions, scoreboards and coverage models.
• Execute directed and constrained-random verification.
• Analyse coverage and debug RTL and verification issues.
• Support subsystem and system-level integration activities.
• Contribute to automation, regression and CI workflows.
• Participate in design reviews and verification sign-off.
• Mentor and support junior colleagues.

Skills

SystemVerilog & UVM

RTL verification

Cross-team collaboration

Linux scripting

AI for verification

Analytical problem solving

Debugging skills

Python/Tcl/Bash scripting

Education

Electronic Engineering or Computer Engineering

Tools

Python

Tcl

Bash

Job description

Senior Verification Engineer

Department: Hardware

Employment Type: Full Time

Location: Cambridge

Description

Our RTL team delivers efficient ASIC and FPGA implementations of advanced communications algorithms, working across IP development, integration and verification. To support this work, we are looking for a Senior Verification Engineer to support the complete UVM verification of Accelercomm IP.

Purpose: Responsible for verification of RTL implementations for advanced wireless communications IP and modem subsystems, ensuring designs meet functional, performance and quality requirements prior to FPGA deployment and ASIC tape-out.

Key Responsibilities

• Develop verification plans from design and architecture specifications.


• Create and maintain SystemVerilog/UVM verification environments.


• Develop testbenches, assertions, scoreboards and coverage models.


• Execute directed and constrained-random verification.


• Analyse coverage and debug RTL and verification issues.


• Support subsystem and system-level integration activities.


• Contribute to automation, regression and CI workflows.


• Participate in design reviews and verification sign-off.


• Mentor and support junior colleagues

Skills, Knowledge & Expertise

Required

• Degree in Electronic Engineering, Computer Engineering or a related discipline.


• At least 3 years experience verifying digital ASIC and/or FPGA designs.


• Strong SystemVerilog and UVM skills.


• Understanding of RTL design principles and hardware implementation.


• Experience with coverage-driven and assertion-based verification.


• Linux proficiency and scripting skills (Python, Tcl or Bash).


• Strong analytical, debugging and problem-solving skills.


• Experience using AI to accelerate verification without sacrificing quality


• Ability to work across multiple teams

Desirable

• Experience in 4G/5G, NTN, satellite communications or DSP systems.


• Knowledge of modem architectures and Layer 1 processing.


• Experience with Formal Verification, FPGA prototyping and CI environments.


• Familiarity with MATLAB or equivalent modelling tools.

Job Benefits

We pay competitive salaries which depend on skills and experience. We offer a bonus scheme which pays up to 20% of salary annually, depending on performance. This is in addition to EMI share options, issued periodically. We offer a range of good quality company benefits including pension and private health insurance. We operate flexible working hours and offer hybrid working.