Senior/Staff CPU Physical Design Engineer - High-Performance Compute / Semiconductors

European Tech Recruit; Cambridge; Presencial; GBP 90.000 - 130.000; Jornada completa

Descripción de la vacante

European Tech Recruit is assisting a global semiconductor leader in Cambridge, UK, to hire a Senior/Staff CPU Physical Design Engineer for block-level implementation on high-performance compute cores. The role is fully onsite in Cambridge with collaboration across RTL, CAD, and SoC teams.

The candidate will drive timing closure, signoff, and power integrity while advancing design flows and automation for advanced nodes (7nm and below).

Formación

• Experience in physical design for CPUs.
• Experience on 7nm and below.
• On-site Cambridge.
• Strong timing closure and PPA focus.

Responsabilidades

• Own or contribute to CPU block implementation from RTL/netlist to GDS.
• Drive timing closure and physical implementation convergence.
• Debug and resolve issues across timing, congestion, clocking, IR drop, power integrity, EM, DRC/LVS.
• Collaborate with RTL, architecture, CAD, SoC, and post-silicon teams to improve design quality and PPA.
• Develop and enhance physical design flows, automation, and methodologies.

Conocimientos

Physical design

Synthesis

Floorplanning

Placement/CTS

Routing

Timing closure

Power integrity

ECOs

DRC/LVS

EDA tools

Genus

Innovus

Fusion Compiler

PrimeTime

Tempus

Voltus

RedHawk

TCL scripting

Herramientas

Genus

Innovus

Fusion Compiler

PrimeTime

Tempus

Voltus

RedHawk

Descripción del empleo

Senior/Staff CPU Physical Design Engineer - High-Performance Compute / Semiconductors

We are partnered with a global leader in semiconductor and wireless technology innovation. The team is looking to hire a Senior or Staff Server CPU Physical Design Engineer to own block-level physical implementation for next-generation, high-performance custom CPU cores targeting advanced compute and server-class platforms.

This is a permanent, fully onsite opportunity based in Cambridge, UK.

Key responsibilities for this CPU Physical Design Engineer position:

• Own or contribute to CPU block implementation from RTL/netlist to GDS
• Drive timing closure and physical implementation convergence across multiple modes, corners, and operating conditions.
• Debug and resolve complex implementation issues across timing, congestion, clocking, IR drop, power integrity, EM, and DRC/LVS.
• Collaborate with RTL, architecture, circuits, CAD, SoC, and post-silicon teams to improve design quality and PPA.
• Develop and enhance physical design flows, automation, and methodologies.

Key requirements:

• Strong experience in physical design — synthesis, floorplanning, placement, CTS, routing, timing closure, ECOs, and signoff.
• Solid understanding of STA and timing closure methodologies, including PPA trade-offs.
• Hands-on experience with industry-standard EDA tools — Genus, Innovus, Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, or equivalent.
• Scripting experience in TCL, Python, or Perl.
• Experience on CPU cores, advanced nodes (7nm and below), or low-power design techniques advantageous.

Keywords: Server CPU Physical Design Engineer / Physical Design / Place & Route / Floorplanning / CTS / Timing Closure / STA / ECO / Synthesis / Innovus / Fusion Compiler / PrimeTime / Tempus / Voltus / RedHawk / DRC / LVS / Low Power / CPU / High Performance Compute / Advanced Nodes / TCL / Python

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