Senior Physical Design Engineer

IC Resources; Farnborough; On-site; GBP 65,000 - 85,000; Full time

Job summary

A leading international space technology organisation in Farnborough is looking for a Senior Physical Design Engineer to support the development of complex satellite SoCs. This role involves managing physical implementation, including floorplanning and timing closure, and requires expertise in ASIC development. Candidates should have a strong background in advanced node physical design and be familiar with industry-standard tools such as Cadence or Synopsys. A scripting capability is also essential.

Qualifications

• Strong background in ASIC development as a Senior Physical Design Engineer.
• Proven experience in physical design flows for advanced nodes (28nm or below).
• Solid understanding of floorplanning, timing closure, and physical sign-off.

Responsibilities

• Drive physical implementation of complex SoCs including integration of custom blocks.
• Manage floorplanning, place & route, and clock tree implementation strategies.
• Lead block-level timing closure and support full-chip timing convergence.

Skills

Senior Physical Design Engineering

ASIC development

Floorplanning

Place & Route (P&R)

Clock Tree Synthesis (CTS)

Static Timing Analysis (STA)

Scripting (Tcl, Python, Perl)

Tools

Cadence implementation tools

Synopsys implementation tools

Job description

Senior Physical Design Engineer - Farnborough

A leading international space technology organisation is continuing to expand its advanced ASIC capability and is seeking a Senior Physical Design Engineer to support the development of complex satellite SoCs.

This opportunity sits within our client’s semiconductor division, focused on high-performance communication devices used in space and ground-based systems. The team works on technically demanding mixed-signal ASICs in advanced technology nodes, including devices designed for high-reliability environments.

As a Senior Physical Design Engineer, you will contribute across the full physical implementation cycle, from RTL handoff through to tape-out and production. You will take ownership of block-level implementation while contributing to chip-level integration and sign-off activities.

What you will be doing:

• Driving physical implementation of complex SoCs, including integration of custom blocks and third-party IP
• Managing floorplanning, place & route and clock tree implementation strategies
• Leading block-level timing closure and supporting full-chip timing convergence
• Developing and refining implementation constraints in collaboration with RTL teams
• Supporting DFT insertion and ensuring smooth physical integration at chip level
• Running and analysing extraction, power and physical verification checks prior to sign-off
• Working closely with cross-functional engineering teams and external partners to optimise flow and delivery

Skills and experience required:

• Strong background as a Senior Physical Design Engineer within ASIC development
• Proven experience across advanced node physical design flows (28nm or below preferred)
• Solid understanding of synthesis, floorplanning, P&R, CTS, STA, timing closure and physical sign-off
• Experience with industry-standard Cadence or Synopsys implementation toolchains
• Good knowledge of power planning and analysis in complex SoCs
• Scripting capability (Tcl, Python, Perl or similar) to support flow automation
• Confident communicator, comfortable interfacing with design, verification and third-party IP team

This is a strong opportunity for an experienced Senior Physical Design Engineer looking to work on technically ambitious silicon programmes within a globally recognised space-focused organisation.

Tel - 01189073075

LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/