Senior CPU Physical Design Engineer – High-Performance Cores

IC Resources; Cambridgeshire and Peterborough; On-site; GBP 70,000 - 100,000; Full time

Job summary

IC Resources is seeking a Phsyical Design Engineer to drive end-to-end CPU block implementation on cutting-edge nodes. You will collaborate with RTL, architecture and methodology teams to optimize performance, power and area while meeting aggressive project schedules.

The role requires hands-on experience with floorplanning, CTS, place-and-route and sign-off, plus scripting in TCL, Python, or Perl to enhance flows and automation. A strong background in ASIC/CPU/SoC physical design is essential.

Qualifications

• Degree in Electrical/Electronic Engineering or Computer Engineering.
• Proven hands-on experience in physical design for ASIC/CPU/SoC.
• Experience across floorplanning, placement and routing, CTS and sign-off.
• Familiar with Innovus, ICC2, Fusion Compiler (or equivalent).
• Strong scripting skills with TCL, Python or Perl.

Responsibilities

• Drive physical implementation of CPU blocks from synthesis to sign-off.
• Own floorplanning, power planning, placement, CTS and routing.
• Collaborate with RTL, architecture, STA and methodology teams to optimize performance, power and area.
• Identify and resolve timing, congestion, power, and DRC/LVS issues.
• Develop automation and flows using TCL, Python or Perl.
• Support design closure across advanced process technologies.
• Work with cross-functional teams to deliver silicon on aggressive schedules.

Skills

Physical design

Floorplanning

Place & route

Timing closure

Power/area optimization

Scripting (TCL/Python/Perl)

Education

Electrical/Electronic Engineering or Computer Engineering degree

Tools

Innovus

ICC2

Fusion Compiler

Job description

IC Resources is seeking a Phsyical Design Engineer to drive end-to-end CPU block implementation on cutting-edge nodes. You will collaborate with RTL, architecture and methodology teams to optimize performance, power and area while meeting aggressive project schedules.

The role requires hands-on experience with floorplanning, CTS, place-and-route and sign-off, plus scripting in TCL, Python, or Perl to enhance flows and automation. A strong background in ASIC/CPU/SoC physical design is essential.