Senior RTL Design Engineer – CPU Cores| Equity + Relocation

IC Resources; Greater London; On-site; GBP 90,000 - 120,000; Full time

Benefits offered by this job

Annual bonus

Equity / share options

Career development opportunities

Job summary

IC Resources is partnering with a global semiconductor leader to hire a Staff/Senior Staff RTL Design Engineer in the Greater London area. You will design industry-leading CPU cores, across the full design lifecycle, collaborating with world-class architects and design engineers on technically demanding projects.

The role requires 6+ years of RTL experience, strong Verilog/SystemVerilog/VHDL skills, and a solid software background (C/C++/Python) plus DSLs.

Qualifications

• Bachelor's or Master's degree in CS/CE/EE or equivalent experience.
• 6+ years of RTL design experience in CPU projects.
• Experience with Verilog, SystemVerilog or VHDL for CPU cores.
• Strong software background: C/C++/Python; DSL knowledge.
• Familiarity with RISC-V and verification methodologies like UVM.

Responsibilities

• Design and implement RTL for CPU cores across full design cycle.
• Collaborate with architects and engineers on challenging projects.
• Develop testbenches and perform functional coverage.
• Contribute to verification strategies and performance optimisations.

Skills

RTL design

Verilog/SystemVerilog/VHDL

C/C++/Python

DSLs

Unit tests / TDD

UVM / verification

RISC-V knowledge

CPU microarchitecture

Testbench development

Attention to detail

Education

Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related discipline

Job description

IC Resources is partnering with a global semiconductor leader to hire a Staff/Senior Staff RTL Design Engineer in the Greater London area. You will design industry-leading CPU cores, across the full design lifecycle, collaborating with world-class architects and design engineers on technically demanding projects.

The role requires 6+ years of RTL experience, strong Verilog/SystemVerilog/VHDL skills, and a solid software background (C/C++/Python) plus DSLs.