Senior Physical Design & STA Engineer – SoC Layout (3 yrs)

Sevya Multimedia; Girton; On-site; GBP 7,100 - 12,000; Full time

Job summary

Sevya Multimedia is hiring a full-time, on-site Physical Design Engineer to lead floorplanning, placement, CTS, routing and layout optimization for complex SoCs. You will run static timing analyses, assess signal integrity, power, and physical verification reports, and implement fixes to meet performance targets.

You will collaborate with architecture and RTL teams, maintain CAD flows, prepare constraint files, and support tape-out activities while documenting methodologies and participating in

Qualifications

• Hands-on experience in physical design, STA, and layout for semiconductor devices.
• Proficiency with CAD tools for physical design and timing analysis.
• Experience with floorplanning, CTS, routing, DRC/LVS, and timing closure.

Responsibilities

• Perform physical design implementation tasks: floorplanning, placement, CTS, routing, layout optimization.
• Run and analyze static timing, signal integrity, power, and physical verification reports.
• Collaborate with architecture and RTL teams; prepare constraint files and CAD flows.
• Support tape-out activities and document methodologies.

Skills

CAD tools

Static Timing Analysis

Layout optimization

Floorplanning

Python scripting

Team collaboration

Digital SoC architecture

Education

Bachelor’s or Master’s degree in Electrical/Electronics/CE

Tools

Cadence

Synopsys

Job description

Sevya Multimedia is hiring a full-time, on-site Physical Design Engineer to lead floorplanning, placement, CTS, routing and layout optimization for complex SoCs. You will run static timing analyses, assess signal integrity, power, and physical verification reports, and implement fixes to meet performance targets.

You will collaborate with architecture and RTL teams, maintain CAD flows, prepare constraint files, and support tape-out activities while documenting methodologies and participating in