Principal SoC Physical Design Architect - Tape-Out Leader

Aion Silicon Ltd; West of England; Presencial; GBP 110.000 - 180.000; Jornada completa

Descripción de la vacante

Aion Silicon Ltd is seeking a Principal Engineer for SoC Physical Design or Chip-Level Expert to lead ASIC/SoC implementation from architecture to tape-out. You will drive full-chip physical design, floorplanning, clocking, place-and-route, and signoff while coordinating with Architecture, RTL, Verification, DFT, STA, and Packaging teams.

This hands-on leader will set methodologies, champion BKMs, define milestones, manage dependencies, and mentor engineers across distributed teams.

Formación

• 15+ years of ASIC/SoC Physical Design experience.
• Proven track record of multiple successful SoC tape-outs.
• Strong understanding of floorplanning, clock distribution, power networks, I/O planning, and hard IP integration.
• Experience with multi-volt/multi-clock-domain designs and ESD strategies.
• Knowledge of hierarchical/top-down design methodologies and timing/convergence strategies.
• Experience integrating IPs from internal and external vendors and signoff ownership.

Responsabilidades

• Partner with Front-End and Architecture to guide physical design early in development.
• Lead full-chip physical implementation activities including floorplanning, power planning, clock implementation, place-and-route, timing closure, and signoff.
• Drive physical design methodologies, BKMs, checklists, and implementation guidelines across projects.
• Serve as the technical focal point for physical design execution and coordinate activities across blocks, subsystems, and top-level implementations.
• Define project milestones, track progress, manage dependencies, and drive tape-out schedules.
• Collaborate with STA, DFT, RTL, Verification, Power Integrity, and Packaging teams to meet project goals.
• Mentor engineers and contribute to continuous improvement of design methodologies and automation flows.

Conocimientos

Leadership

Cross-functional leadership

Mentoring

Problem solving

Educación

B.Tech / M.Tech in Electrical Engineering / Electronics / Computer Engineering

Herramientas

Calibre

IC Validator

Pegasus

RedHawk

Voltus

PrimePower

TCL

Perl

Python

Shell scripting

Descripción del empleo

Aion Silicon Ltd is seeking a Principal Engineer for SoC Physical Design or Chip-Level Expert to lead ASIC/SoC implementation from architecture to tape-out. You will drive full-chip physical design, floorplanning, clocking, place-and-route, and signoff while coordinating with Architecture, RTL, Verification, DFT, STA, and Packaging teams.

This hands-on leader will set methodologies, champion BKMs, define milestones, manage dependencies, and mentor engineers across distributed teams.