Senior Physical Design Engineer

MRL Consulting Group | Global Niche Technology Recruitment; United Kingdom; On-site; GBP 90,000 - 135,000; Full time

Job summary

MRL Consulting Group | Global Niche Technology Recruitment is recruiting on behalf of a leading satellite communications organisation for an experienced Senior Physical Design Engineer to join their multinational Physical Design team.

You will work on state-of-the-art satellite SoCs, including complex digital and analogue modules and next-generation radiation-hardened satellite modems, using advanced process technologies and industry-standard EDA tools.

Qualifications

• 8+ years of experience in physical design for ASIC/SoC projects.
• Strong background in RTL-to-GFX and tape-out flows.
• Experience with deep sub-micron technologies (28nm or below).
• Proficient in Cadence or Synopsys tool flows and scripting (Tcl/Python).
• Experience collaborating with IP vendors and external partners.

Responsibilities

• Deliver physical implementation of complex SoCs, including digital and analogue blocks and test chips.
• Own block-level timing closure and manufacturing sign-off, including power planning and analysis.
• Develop timing constraints with RTL/Logic Design teams at block and chip levels.
• Implement DFT structures and support chip-level integration, simulation and verification.
• Improve design scripts and tool flows for efficiency and reliability.
• Collaborate with design teams, IP/library vendors, EDA vendors and external design service providers.

Skills

Physical design

ASIC/SoC flow

Synthesis & P&R

Timing closure

Power analysis

DFT/DFM

Parasitic extraction

Cadence / Synopsys

Scripting (Tcl/Python)

Team collaboration

Education

Bachelor's degree in EE/CS

Tools

Cadence

Synopsys

Job description

We are recruiting on behalf of our client, a leading organisation in the satellite communications industry, for an experienced Senior Physical Design Engineer to join their multinational Physical Design team.

This is an opportunity to work on state-of-the-art satellite SoCs, including complex digital and analogue modules and next-generation radiation-hardened satellite modems, using leading-edge process technologies and industry-standard EDA tools.

Key Responsibilities

• Deliver physical implementation of complex SoCs, VLSI devices and test chips, integrating custom designs and third-party IP.
• Own block-level timing closure and manufacturing sign-off, including power planning and analysis.
• Develop timing constraints with RTL/Logic Design teams at block and chip level.
• Implement DFT structures and support chip-level integration, simulation and verification.
• Contribute to improving design scripts and tool flows.
• Collaborate with design teams, IP/library suppliers, EDA vendors and external design service providers.

About You

• 8+ years' experience as a Physical Design Engineer.
• Bachelor’s degree in Electrical Engineering, Computer Science or a related field.
• Strong experience across the ASIC/COT physical design flow, including synthesis, floor-planning, P&R, CTS, parasitic extraction, STA, timing closure, physical verification, power analysis, formal verification, DFT/DFM and ATPG.
• Experience with deep sub-micron technologies (28nm or below).
• Experience with Cadence or Synopsys EDA tool flows.
• Strong scripting skills using Tcl, Python, Perl or similar.
• Strong analytical and problem-solving abilities.
• Experience working with cross-functional design teams, third-party IP suppliers and external design partners.