Senior FPGA Engineer - Ultra-Low Latency (Hybrid Contract)

Adepta Partners; Greater London; Hybrid; GBP 92,000 - 138,000; Full time

Job summary

Adepta Partners is seeking a Senior FPGA Engineer to join a high-performance team in London on a hybrid basis. This contract role focuses on ultra-low-latency FPGA solutions for the financial sector, with a hands-on design and debugging emphasis.

The position is outside IR35, a 6-month initial term, with a competitive day rate. Ideal candidates have 5+ years in FPGA design, expertise in VHDL/Verilog and Vivado, and strong networking protocol knowledge.

Qualifications

• 5+ years commercial FPGA design experience.
• VHDL and/or Verilog development skills.
• Experience with AMD/Xilinx Vivado, synthesis, timing closure and hardware debugging.
• Knowledge of TCP/UDP, Ethernet, PCIe and DMA.
• Python and Linux experience for testing and automation.
• Experience with low-latency systems in financial trading, capital markets or telecommunications.

Skills

FPGA design

Low-latency systems

Testing & automation

Tools

Vivado

Linux

Python

Job description

Adepta Partners is seeking a Senior FPGA Engineer to join a high-performance team in London on a hybrid basis. This contract role focuses on ultra-low-latency FPGA solutions for the financial sector, with a hands-on design and debugging emphasis.

The position is outside IR35, a 6-month initial term, with a competitive day rate. Ideal candidates have 5+ years in FPGA design, expertise in VHDL/Verilog and Vivado, and strong networking protocol knowledge.