Senior Digital ASIC Design Engineer

IC Resources; Southampton; On-site; GBP 90,000 - 120,000; Full time

Job summary

IC Resources in Southampton is seeking a Senior Digital ASIC Design Engineer to deliver high‑performance RTL for satellite communications, ASIC and FPGA platforms, translating algorithms into efficient hardware.

You will collaborate with Systems, Architecture, Verification and Physical Design teams from spec to implementation, optimise timing, power and area, and contribute to design methodologies. The role can also suit Bristol or Cambridge locations.

Qualifications

• Proven experience in RTL design for ASIC/FPGA.
• Strong Verilog or SystemVerilog skills and RTL debugging.
• Experience with synthesis, timing analysis and power optimisation.
• Experience collaborating across multidisciplinary hardware teams.
• Solid documentation and communication skills.

Responsibilities

• Translate system and algorithm requirements into RTL architectures.
• Design and implement complex digital logic for ASIC/FPGA.
• Develop testbenches and verification environments.
• Deploy designs onto FPGA platforms for validation.
• Optimise designs for timing, throughput, area and power.
• Collaborate with Verification, Physical Design and Systems teams.
• Contribute to design methodologies and processes.

Skills

RTL design

Verilog/SystemVerilog

ASIC/FPGA design

Synthesis

Timing analysis

Power optimisation

Documentation

Cross-functional teamwork

Simulation tools

Industry standard tools

Tools

ModelSim

Vivado

Quartus

Synopsys

Job description

Senior Digital ASIC Design Engineer - Southampton

Join an innovative semiconductor company developing next generation communications technology for satellite based 5G connectivity.

This is an opportunity to work on complex digital hardware, developing ASIC and FPGA solutions for demanding communications applications. You’ll translate advanced algorithms into efficient RTL, contributing to high performance IP and complete system solutions.

Working within a multidisciplinary engineering team, you’ll collaborate with Systems, Architecture, Verification and Physical Design teams from specification through to implementation and validation.

Responsibilities

• Translate system and algorithm requirements into efficient RTL micro architectures
• Design and implement complex digital logic for ASIC and FPGA platforms
• Develop simulation environments and testbenches to verify functionality
• Deploy designs onto FPGA platforms for validation and system integration
• Optimise designs for timing, throughput, area and power
• Work closely with Verification, Physical Design and Systems teams
• Contribute to design methodologies and engineering processes

What they’re looking for

• Strong experience designing complex ASIC and/or FPGA systems
• Excellent RTL skills using Verilog or SystemVerilog
• Experience optimising high throughput designs for performance and resource utilisation
• Knowledge of synthesis, timing analysis and power optimisation
• Experience working across multidisciplinary hardware teams
• Strong technical documentation skills
• Experience with industry standard simulation and synthesis tools

This role can also be based in Bristol or Cambridge.

Tel - 01189073075

LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/