Application Specific Integrated Circuit Design Engineer

Yoh, A Day & Zimmermann Company; West of England; On-site; GBP 90,000 - 130,000; Full time

Job summary

Yoh, A Day & Zimmermann Company is assembling a digital hardware team in Bristol to deliver FPGA and ASIC projects. You will work with algorithm and system architecture teams to translate requirements into RTL implementations, covering simulation, synthesis, timing closure and hardware deployment.

Levels range from experienced IC engineers to principal engineers and technical leads, with opportunities to influence team practices and delivery of larger IP blocks.

Qualifications

• Proven experience designing complex FPGA/ASIC RTL.
• Strong knowledge of Verilog or SystemVerilog and RTL design methods.

Responsibilities

• Design RTL for FPGA/ASIC products and optimize for performance, area and power.
• Develop verification testbenches, simulate and synthesis flows.
• Collaborate with architecture, design, verification and implementation teams to deliver IP.
• Mentor junior engineers and contribute to technical direction as needed.

Skills

Verilog

SystemVerilog

RTL design

FPGA/ASIC

Job description

Mid, Senior, Principal & Technical Lead levels

A new digital hardware team is being built in Bristol.

Not an engineering outpost where every important decision is made elsewhere. The first hires will help shape the team, its working practices and how complex FPGA and ASIC products are delivered.

The company develops hardware-accelerated Layer 1 technology for 5G and satellite communications. Its IP is being developed for use within space-based communications systems, creating engineering challenges around throughput, latency, power consumption and efficient use of hardware resources.

We are looking for digital design engineers at several levels, from experienced individual contributors through to principal engineers and technical leads.

You will work with algorithm and system architecture teams to turn communications requirements into practical microarchitectures and RTL implementations. The work covers FPGA and ASIC design, simulation, testbench creation, synthesis, timing closure, optimisation, hardware deployment and system integration.

The core experience

• Verilog or SystemVerilog RTL design for complex FPGA or ASIC products
• Delivery of digital hardware through implementation, simulation and synthesis
• Timing, power and resource optimisation for high-throughput systems
• Collaboration across architecture, design, verification and implementation teams

Depending on your level, you may also contribute to technical direction, mentor other engineers, improve development methodology or lead the delivery of larger pieces of IP.

Experience in communications signal processing, modems, DSP, AMBA protocols, UVM, SystemC, PCIe, JESD or AMD FPGA platforms would be useful, but direct wireless experience is not essential.

What matters more is your ability to take a demanding technical requirement and turn it into hardware that meets its performance, power and implementation constraints.

The technology already exists. The commercial demand is creating the need to scale it.

For the engineers joining the Bristol team, that means an opportunity to influence what is built, how it is implemented and how the new engineering group develops.