Senior DFT Architect for AI Accelerators (Equity)

Fractile; West of England; On-site; GBP 120,000 - 160,000; Full time

Job summary

Fractile in the United Kingdom is seeking an experienced DFT Architect to lead the design of scanning, compression, and ATPG for a next‑generation AI accelerator SoC. The role combines architectural planning with hands‑on debugging, requiring close collaboration with RTL and physical design teams.

You will define the DFT strategy, sign‑off criteria, and integrate DFT flows across the EDA environment, mentoring engineers and driving test patterns for production yield.

Qualifications

• 8+ years of DFT experience on complex ASIC/SoC designs.
• Proven ownership of DFT architecture on at least one large tapeout.
• Deep expertise in scan, compression, ATPG, and MBIST.

Responsibilities

• Own and define the DFT architecture for a large AI accelerator SoC.
• Set DFT strategy, methodology, flow and signoff criteria.
• Drive integration of DFT tools and flows into the overall EDA environment.
• Define hierarchical DFT approach for multi-core designs and large memory systems.
• Define scan architecture, compression strategy, and ATPG approach.
• Define memory test and repair strategy for large embedded RAM.
• Establish power-aware and at-speed test strategies.
• Work closely with RTL and physical design to ensure clean DFT integration and timing closure.
• Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test and yield ramp.
• Mentor and guide DFT engineers

Skills

DFT strategy

Architectural thinking

Timing closure

Mentoring

Tools

Synopsys

Tessent

Job description

Fractile in the United Kingdom is seeking an experienced DFT Architect to lead the design of scanning, compression, and ATPG for a next‑generation AI accelerator SoC. The role combines architectural planning with hands‑on debugging, requiring close collaboration with RTL and physical design teams.

You will define the DFT strategy, sign‑off criteria, and integrate DFT flows across the EDA environment, mentoring engineers and driving test patterns for production yield.