Senior DFT Architect – AI Accelerator SoC

Fractile; Greater London; On-site; GBP 90,000 - 130,000; Full time

Benefits offered by this job

Equity & Ownership

Private Medical, Dental & Vision

Contributory Pension

25 Days Holiday + Bank Holidays

Job summary

Fractile in the United Kingdom is seeking a Senior DFT Architect to own the DFT architecture for a large AI accelerator SoC, driving scan, compression, MBIST and ATPG strategies across complex multi-core designs.

You will partner with RTL and physical design to ensure clean DFT integration, timing closure and power-aware test across production ramp, while mentoring junior DFT engineers.

Join a fast-moving team building hardware to unlock AI performance at scale.

Qualifications

• 8+ years of DFT experience on ASIC/SoC designs.
• Own DFT architecture on at least one large tapeout.
• Deep expertise in scan, compression, ATPG, MBIST.
• Experience with industry tools such as Synopsys/Tessent.
• Strong understanding of clocking, resets, power domains, and physical constraints.
• Experience with silicon bring-up, debug, and yield ramp.

Responsibilities

• Own and define the DFT architecture for a large AI accelerator SoC.
• Set DFT strategy, methodology, flow and signoff criteria.
• Drive integration of DFT tools into the EDA environment.
• Define hierarchical DFT approach for multi-core designs and large memory systems.
• Define scan architecture, compression strategy, and ATPG approach.
• Define memory test and repair strategy for large embedded RAM.
• Establish power-aware and at-speed test strategies.
• Work closely with RTL and physical design for clean DFT integration and timing closure.
• Work with test and product teams to bring up ATPG patterns on ATE for production test.
• Mentor and guide DFT engineers.

Skills

DFT architecture

ASIC/SoC experience

ATPG/MBIST

Clocking & power domains

Yield ramp debugging

Tools

Synopsys tools

Tessent

Job description

Fractile in the United Kingdom is seeking a Senior DFT Architect to own the DFT architecture for a large AI accelerator SoC, driving scan, compression, MBIST and ATPG strategies across complex multi-core designs.

You will partner with RTL and physical design to ensure clean DFT integration, timing closure and power-aware test across production ramp, while mentoring junior DFT engineers.

Join a fast-moving team building hardware to unlock AI performance at scale.