Senior/Principal DFT Engineer

Fractile; Greater London; In loco; GBP 90.000 - 130.000; Tempo pieno

Vantaggi offerti da questo lavoro

Equity & Ownership

Private Medical, Dental & Vision

Contributory Pension

25 Days Holiday + Bank Holidays

Descrizione del lavoro

Fractile in the United Kingdom is seeking a Senior DFT Architect to own the DFT architecture for a large AI accelerator SoC, driving scan, compression, MBIST and ATPG strategies across complex multi-core designs.

You will partner with RTL and physical design to ensure clean DFT integration, timing closure and power-aware test across production ramp, while mentoring junior DFT engineers.

Join a fast-moving team building hardware to unlock AI performance at scale.

Competenze

• 8+ years of DFT experience on ASIC/SoC designs.
• Own DFT architecture on at least one large tapeout.
• Deep expertise in scan, compression, ATPG, MBIST.
• Experience with industry tools such as Synopsys/Tessent.
• Strong understanding of clocking, resets, power domains, and physical constraints.
• Experience with silicon bring-up, debug, and yield ramp.

Mansioni

• Own and define the DFT architecture for a large AI accelerator SoC.
• Set DFT strategy, methodology, flow and signoff criteria.
• Drive integration of DFT tools into the EDA environment.
• Define hierarchical DFT approach for multi-core designs and large memory systems.
• Define scan architecture, compression strategy, and ATPG approach.
• Define memory test and repair strategy for large embedded RAM.
• Establish power-aware and at-speed test strategies.
• Work closely with RTL and physical design for clean DFT integration and timing closure.
• Work with test and product teams to bring up ATPG patterns on ATE for production test.
• Mentor and guide DFT engineers.

Conoscenze

DFT architecture

ASIC/SoC experience

ATPG/MBIST

Clocking & power domains

Yield ramp debugging

Strumenti

Synopsys tools

Tessent

Descrizione del lavoro

About FractileFractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.

The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.

Key Responsibilities

• Own and define the DFT architecture for a large AI accelerator SoC (scan, compression, MBIST, LBIST, boundary scan)
• Set DFT strategy, methodology, flow and signoff criteria
• Drive integration of DFT tools and flows into the overall EDA environment
• Define hierarchical DFT approach for multi-core designs and large memory systems
• Define scan architecture, compression strategy, and ATPG approach
• Define memory test and repair strategy for large embedded RAM
• Establish power-aware and at-speed test strategies
• Work closely with RTL and physical design to ensure clean DFT integration and timing closure
• Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test and yield ramp
• Mentor and guide DFT engineers

Required Experience

• Strong experience in DFT for complex ASIC/SoC designs (typically 8+ years)
• Proven ownership of DFT architecture on at least one large tapeout
• Deep expertise in scan, compression, ATPG, and MBIST
• Experience with industry tools (Synopsys or Tessent)
• Strong understanding of clocking, resets, power domains, and physical constraints
• Experience with silicon bring-up, debug, and yield ramp

Profile

• Comfortable owning ambiguous, high-impact problems
• Balances architectural thinking with hands‑on execution
• Sets direction while staying close to implementation details

What We Offer

• Competitive salary: A competitive salary reflective of your experience and the specialist nature of the role.
• Equity & Ownership: meaningful equity so everyone shares in the value creation
• Benefits: Private Medical, Dental and Vision, Contributory Pension, 25 Days holiday plus bank holidays and Life/Critical Illness Insurance.
• Diverse & fun office: we believe the hardest problems get solved by the broadest range of minds. We are committed to Equal Employment Opportunity through attracting and retaining a diverse team and building an inclusive environment.

the company is seeking to increase the clock speed of global progress, one chip at a time. We’ve recently raised $220M from investors including Founders Fund and Accel and our most important work lies ahead. Join us!

Export controls

Our work involves technologies subject to UK, US and other international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We'll be transparent about this throughout the hiring process.

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