Senior ASIC Verification & Design Lead

Synopsys, Inc.; United Kingdom; On-site; GBP 70,000 - 110,000; Full time

Job summary

Synopsys, Inc. is seeking an enthusiastic ASIC Digital Design Engineer with a passion for cutting-edge technology to translate high-level requirements into robust digital designs.

You will verify complex Interface IP, develop testbenches, and drive coverage closure in collaboration with cross-functional teams. The role emphasizes strong SystemVerilog/UVM expertise, mentoring junior engineers, and contributing to design and verification reviews to ensure high-quality IP products for multiple

Qualifications

• Experience with developing testbenches in SystemVerilog/UVM.
• Experience with interface IP verification and test plans.
• Strong debugging and analytical skills.

Responsibilities

• Designing and implementing verification environments for Interface IP protocols.
• Collaborating with design and architecture teams to fix bugs.
• Verifying complex digital IP including test plans and coverage analysis.
• Mentoring junior verification engineers.
• Documenting design specs, test plans, and verification reports.
• Conducting design and verification reviews.

Skills

Digital design

Verification methodologies

SystemVerilog

UVM

SVA

Python

Perl

Attention to detail

Communication

Mentoring

Tools

SystemVerilog

UVM

SVA

Job description

Synopsys, Inc. is seeking an enthusiastic ASIC Digital Design Engineer with a passion for cutting-edge technology to translate high-level requirements into robust digital designs.

You will verify complex Interface IP, develop testbenches, and drive coverage closure in collaboration with cross-functional teams. The role emphasizes strong SystemVerilog/UVM expertise, mentoring junior engineers, and contributing to design and verification reviews to ensure high-quality IP products for multiple