Senior ASIC RTL Front-End Engineer — SoC Innovation

Capgemini Engineering; England; On-site; GBP 90,000 - 120,000; Full time

Benefits offered by this job

Employee share ownership plans

Savings schemes

Referral bonuses

Social and cultural activities

Job summary

Capgemini Engineering seeks an Expert Front-End ASIC RTL Designer to join a team working on advanced semiconductor technologies. You will design, develop and debug ASIC IPs, collaborating across design, verification and software teams to deliver high-quality SoCs.

The role involves RTL design in Verilog/SystemVerilog/VHDL, IP integration at the SoC level, and adherence to DFT, CDC, RDC, Lint, and UPF guidelines in a dynamic engineering environment.

Qualifications

• 15+ years of experience in IP design and verification (digital or mixed-signal).
• Experience with IP integration at SoC/partition/FPGA level.

Responsibilities

• Study and specify digital or mixed-signal IPs used in ASIC components.
• Define and analyse SoC architectures.
• Design or adapt IPs in RTL while following DFT, CDC, RDC, Lint, UPF rules.
• Integrate IPs within a partition or at SoC level.
• Collaborate with Verification, Integration, Physical Design, Software/Firmware, Product Engineering and Test teams.

Skills

IP design

IP verification

SoC integration

RTL design

ARM/MIPS/RISC-V

Bus architectures

Memory controllers

Verilog/SystemVerilog/VHDL

Tools

Verilog

SystemVerilog

VHDL

Job description

Capgemini Engineering seeks an Expert Front-End ASIC RTL Designer to join a team working on advanced semiconductor technologies. You will design, develop and debug ASIC IPs, collaborating across design, verification and software teams to deliver high-quality SoCs.

The role involves RTL design in Verilog/SystemVerilog/VHDL, IP integration at the SoC level, and adherence to DFT, CDC, RDC, Lint, and UPF guidelines in a dynamic engineering environment.