Graduate Digital Design Engineer — ASIC & RTL

Renesas Electronics Corporation; City of Edinburgh; On-site; GBP 25,000 - 35,000; Full time

Job summary

Renesas Electronics Corporation is seeking a passionate Graduate Digital Design Engineer to join the hardware development team. You will contribute to the definition and design of complex ASIC systems and gain hands-on experience with industry‑standard tools and methodologies.

You will work on synthesizable RTL in SystemVerilog, collaborate with digital, analogue, and verification teams, and participate in design reviews and sign‑off processes to ensure high-quality deliverables and continuous

Qualifications

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field.
• Internship/industrial placement in related field desirable.
• Strong understanding of digital logic design and HDL familiarity.

Responsibilities

• Interpret high-level requirements to create micro-architecture specifications for digital control and data-path systems.
• Develop synthesizable RTL using SystemVerilog for ASIC digital blocks with constraints.
• Produce design documentation and participate in design reviews and processes.
• Collaborate with digital, analogue, physical design, verification, and DFT teams for integration and sign-off.
• Use sign-off tools to maintain quality of deliverables including LINT, CDC, and formal verification checks.
• Develop and run simulations; debug issues.
• Learn and apply best practices and contribute to process improvements.

Skills

digital logic design

Verilog

VHDL

Python

Git

Linux

communication skills

problem-solving

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Tools

SystemVerilog

Simulation tools

Job description

Renesas Electronics Corporation is seeking a passionate Graduate Digital Design Engineer to join the hardware development team. You will contribute to the definition and design of complex ASIC systems and gain hands-on experience with industry‑standard tools and methodologies.

You will work on synthesizable RTL in SystemVerilog, collaborate with digital, analogue, and verification teams, and participate in design reviews and sign‑off processes to ensure high-quality deliverables and continuous