Senior ASIC/FPGA Design Engineer – Digital Hardware

Yoh, A Day & Zimmermann Company; West of England; On-site; GBP 90,000 - 130,000; Full time

Job summary

Yoh, A Day & Zimmermann Company is assembling a digital hardware team in Bristol to deliver FPGA and ASIC projects. You will work with algorithm and system architecture teams to translate requirements into RTL implementations, covering simulation, synthesis, timing closure and hardware deployment.

Levels range from experienced IC engineers to principal engineers and technical leads, with opportunities to influence team practices and delivery of larger IP blocks.

Qualifications

• Proven experience designing complex FPGA/ASIC RTL.
• Strong knowledge of Verilog or SystemVerilog and RTL design methods.

Responsibilities

• Design RTL for FPGA/ASIC products and optimize for performance, area and power.
• Develop verification testbenches, simulate and synthesis flows.
• Collaborate with architecture, design, verification and implementation teams to deliver IP.
• Mentor junior engineers and contribute to technical direction as needed.

Skills

Verilog

SystemVerilog

RTL design

FPGA/ASIC

Job description

Yoh, A Day & Zimmermann Company is assembling a digital hardware team in Bristol to deliver FPGA and ASIC projects. You will work with algorithm and system architecture teams to translate requirements into RTL implementations, covering simulation, synthesis, timing closure and hardware deployment.

Levels range from experienced IC engineers to principal engineers and technical leads, with opportunities to influence team practices and delivery of larger IP blocks.