Cambridge Principal ASIC/FPGA Design Engineer

Yoh, A Day & Zimmermann Company; Cambridge; Presencial; GBP 70.000 - 100.000; Jornada completa

Descripción de la vacante

Yoh, A Day & Zimmermann Company is building a new digital hardware team in Cambridge to deliver high‑throughput FPGA and ASIC products for 5G and space communications. The engineers will shape the team, practices, and IP delivery, from architecture to hardware deployment.

Roles span mid to principal and technical leads, with opportunities to mentor, influence development methodology, and lead larger IP pieces while collaborating with algorithm teams and system architects.

Formación

• Verilog or SystemVerilog RTL design for complex FPGA or ASIC products.
• Delivery of digital hardware through implementation, simulation and synthesis.
• Timing, power and resource optimisation for high-throughput systems.

Responsabilidades

• Turn communications requirements into hardware microarchitectures and RTL implementations.
• Work across FPGA/ASIC design, simulation, testbench creation, synthesis, timing closure and deployment.
• Collaborate with architecture, design, verification and implementation teams.

Conocimientos

Verilog

SystemVerilog

FPGA design

ASIC design

Timing optimization

Collaboration

Power optimization

Descripción del empleo

Yoh, A Day & Zimmermann Company is building a new digital hardware team in Cambridge to deliver high‑throughput FPGA and ASIC products for 5G and space communications. The engineers will shape the team, practices, and IP delivery, from architecture to hardware deployment.

Roles span mid to principal and technical leads, with opportunities to mentor, influence development methodology, and lead larger IP pieces while collaborating with algorithm teams and system architects.