Digital Design Team Lead - RTL/ASIC FPGA & Leadership

IC Resources; Cambridge; On-site; GBP 90,000 - 140,000; Full time

Job summary

IC Resources is seeking a Principal Design Team Leader in Cambridge to drive a growing hardware team. The role blends hands-on RTL design with technical leadership, architecture input and delivery accountability for complex digital IP across ASIC/FPGA projects.

You will mentor engineers, shape development processes and collaborate with architecture, verification and software teams to meet performance and schedule targets. A senior stakeholder-facing position with impact.

Qualifications

• Experience in RTL design using Verilog and/or SystemVerilog.
• Previous line management or people management experience in engineering.
• Experience leading technical projects and coordinating engineers to delivery.
• Experience with industry standard simulation and synthesis tools.
• Ability to balance hands-on design with leadership and team development.
• Strong communication skills with engineers and senior stakeholders.

Responsibilities

• Lead, mentor and develop a team of digital design engineers.
• Provide technical leadership across ASIC/FPGA projects.
• Remain hands-on with RTL design and contribute to architecture decisions.
• Own project delivery, ensuring performance, quality and schedule.
• Drive timing, power, area and throughput optimisations.
• Collaborate with architecture, verification, software and other disciplines.
• Shape design methodologies and development processes.
• Translate product requirements into technical objectives for hardware.
• Engage with customers and senior stakeholders on technical discussions.
• Identify opportunities to improve development efficiency with new tools and methods.

Skills

RTL design Verilog/SystemVerilog

People management

Project leadership

Simulation tools

Hands-on design

Communication

Job description

IC Resources is seeking a Principal Design Team Leader in Cambridge to drive a growing hardware team. The role blends hands-on RTL design with technical leadership, architecture input and delivery accountability for complex digital IP across ASIC/FPGA projects.

You will mentor engineers, shape development processes and collaborate with architecture, verification and software teams to meet performance and schedule targets. A senior stakeholder-facing position with impact.