Senior ASIC Digital Synthesis Engineer — Flexible Hours

Nordic Semi; West of England; On-site; GBP 70,000 - 110,000; Full time

Benefits offered by this job

Competitive salary

Flexible hours

Medical insurance

Family benefits

Job summary

Nordic Semiconductor is seeking talented engineers with synthesis and STA experience to contribute to the CSSC team and future tape-outs of ultra-low power Wi‑Fi chips. You will impact design flows and silicon quality.

Responsibilities include timing constraints, RTL-to-gate synthesis, comprehensive STA across corners, ECO-driven timing closure, and DFT collaboration. Proficiency with Synopsys/Cadence tools and scripting (TCL, Python) is required. English communication essential.

Qualifications

• BSc/MSc in Electronics Engineering or similar.
• Several years of chip implementation experience.
• Experience with Synopsys and Cadence IC tools.
• Contribution to flow development and setup.
• Knowledge of scripting languages like TCL, Perl, Python or similar.
• Experience using AI-assisted tools to improve design productivity.

Responsibilities

• Develop, refine, and validate timing constraints to ensure accurate implementation and timing analysis
• Perform RTL-to-gate logic synthesis, optimizing designs for performance, power, and area while meeting project requirements
• Conduct comprehensive Static Timing Analysis (STA) to identify, analyze, and resolve timing issues across multiple operating conditions and process corners
• Drive timing closure activities by implementing and evaluating ECOs
• Perform logic equivalence checking to verify RTL, synthesized netlists, and post-ECO implementations
• Execute low-power verification and analysis to ensure power intent compliance
• Collaborate with the DFT team to integrate test structures and ensure manufacturable silicon
• Partner with digital design teams to translate design intent into implementation

Skills

Synthesis

STA

RTL-to-gate

ECO timing

Scripting TCL/Python

AI-assisted EDA

English comms

Education

BSc/MSc Electronics Engineering

Tools

Synopsys tools

Cadence tools

Job description

Nordic Semiconductor is seeking talented engineers with synthesis and STA experience to contribute to the CSSC team and future tape-outs of ultra-low power Wi‑Fi chips. You will impact design flows and silicon quality.

Responsibilities include timing constraints, RTL-to-gate synthesis, comprehensive STA across corners, ECO-driven timing closure, and DFT collaboration. Proficiency with Synopsys/Cadence tools and scripting (TCL, Python) is required. English communication essential.