ASIC Digital Synthesis Engineer

Nordic Semiconductor; West of England; Sur place; GBP 70 000 - 110 000; Plein temps

Avantages offerts par ce poste

Competitive salary with incentive plan

Medical insurance

Family-friendly policies and benefits

Résumé du poste

Nordic Semiconductor seeks talented engineers skilled in synthesis and static timing analysis to advance next-generation ultra-low power Wi‑Fi chips. You will work within the CSSC team on design flows and tape-outs for silicon realization.

You will contribute to timing constraints, ECO-driven timing closure, DFT integration, and collaboration with digital design teams to translate concepts into concrete implementations, while applying scripting skills and AI-assisted tools in a fast-paced,

Qualifications

• Bachelor/Master level electronics engineering degree required.
• Several years of chip implementation experience.
• Experience with Synopsys and Cadence IC implementation and verification/sign-off tools.
• Contribution to design flow development and setup.
• Proficient scripting in TCL, Perl or Python.
• Experience with AI-assisted EDA flows or code/script generation is a plus.
• Excellent written and verbal English communication.

Responsabilités

• Develop, refine, and validate timing constraints for accurate implementation and timing analysis.
• RTL-to-gate synthesis optimizing performance, power, and area.
• Perform comprehensive Static Timing Analysis across corners and operating conditions.
• Drive timing closure by evaluating ECOs to meet performance and schedule targets.
• Perform logic equivalence checking between RTL, nets, and post-ECO implementations.
• Conduct low-power verification to ensure power intent compliance.
• Collaborate with DFT team to integrate test structures and ensure manufacturability.
• Work with design teams to translate intent into implementation with clear feedback.

Connaissances

Synthesis

Static Timing Analysis

Chip implementation

Synopsys tools

Cadence tools

Scripting (TCL/Perl/Python)

AI-assisted design tools

English communication

Formation

BSc/MSc in Electronics Engineering

Outils

Synopsys IC Compiler

Cadence IC/Verification tools

Signoff/verification tools

Description du poste

We are looking to recruit both talented and experienced engineers with knowledge of synthesis and static timing analysis (STA). As part of the Wi-Fi SoC group you will work closely with our Chip Synthesis and Static Check (CSSC) team and make a real contribution to the design flows and future product tape-outs of Nordic Semiconductor’s next generation of world leading ultra-low power Wi-Fi chips

If you are passionate about digital implementation, enjoy solving difficult engineering problems, and thrive in a collaborative environment where your work directly impacts cutting-edge silicon, this is an opportunity to make a meaningful contribution and grow alongside a team of highly skilled semiconductor professionals.

Key responsibilities

• Develop, refine, and validate timing constraints to ensure accurate implementation and timing analysis
• Perform RTL-to-gate logic synthesis, optimizing designs for performance, power, and area while meeting project requirements.
• Conduct comprehensive Static Timing Analysis (STA) to identify, analyze, and resolve timing issues across multiple operating conditions and process corners.
• Drive timing closure activities by implementing and evaluating ECOs, ensuring designs meet performance and schedule targets.
• Perform logic equivalence checking to verify functional consistency between RTL, synthesized netlists, and post-ECO implementations.
• Execute low-power verification and analysis to ensure compliance with power intent specifications and support energy-efficient product development.
• Collaborate closely with the Design-for-Test (DFT) team to integrate test structures, achieve high test coverage, and ensure manufacturable, testable silicon.
• Partner with digital design and architecture teams to translate design intent into implementation, providing feedback and guidance to meet functional, performance, and timing objectives.

Qualification and skills

• BSc/MSc in Electronics Engineering or similar
• Several years of experience in chip implementation
• Experience of relevant Synopsys and Cadence IC implementation and verification / signoff tools
• Contribution to flow development and setup
• Knowledge of scripting languages like TCL, Perl, Python or similar
• Experience using AI-assisted tools to improve design productivity (e.g. AI-driven EDA flows, code/script generation, debug assistance)
• Excellent written and verbal communication skills in English

Personal Skills

The ideal candidate will combine deep technical expertise with a structured and analytical approach to problem-solving. You have strong attention to detail and a team-oriented professional who communicates clearly and effectively with other teams. You take ownership of your work, thrive in a fast-paced development environment, and are motivated by delivering high-quality silicon on schedule. A continuous improvement mindset, combined with scripting skills and curiosity for emerging technologies such as AI-assisted design tools, allows you to drive efficiency and contribute to the evolution of implementation methodologies and design flows.

Working for Nordic

Working at Nordic, you will be inspired and supported to develop yourself. Our teams enjoy a professional and informal working environment. We value and encourage the continuous development of skills and expertise to the highest levels. We are proud of our Norwegian heritage, our highly skilled international workforce, and our world-leading innovation.

We offer a variety of tasks and projects, and the possibility to work alongside some of the world’s most renowned experts within their field. We encourage our employees to question the established and innovate while expecting professionalism, commitment, and the will to learn.

• Competitive salary with short- and long-term incentive plan
• Medical insurance
• Family-friendly policies, insurances, and benefits

Please note that this position might be subject to a background check.