Senior ASIC PD Engineer – Flexible Hours, Low-Power Silicon

Nordic Semiconductor; West of England; On-site; GBP 70,000 - 95,000; Full time

Benefits offered by this job

Incentive plan

Flexible working hours

Medical insurance

Family-friendly policies

Job summary

Nordic Semiconductor is hiring a Physical Design Engineer to transform advanced semiconductor designs into high-performance silicon. You will drive floorplanning, power integrity, and place-and-route, collaborating across design teams to ensure robust tape-out.

You will contribute to PD flow automation, analyze power integrity, and support silicon bring-up. This role values strong English communication and problem-solving in a fast-paced environment.

Qualifications

• BSc or MSc in electronics engineering or related field.
• Proven experience in chip implementation.
• Experience with Synopsys and Cadence IC tools for implementation and signoff.
• Contributed to flow development and setup.
• Proficient in TCL, Perl, Python or similar scripting languages.
• Experience using AI-assisted tools to improve design productivity.
• Excellent written and verbal English communication.

Responsibilities

• Lead floorplanning, macro placement, and voltage region definition.
• Develop and implement robust power distribution networks.
• Execute Place & Route including CTS, congestion optimization, and timing closure.
• Perform physical verification and signoff ensuring foundry readiness.
• Analyze power integrity, IR-drop, electromigration, and reliability.
• Drive ECOs and late-stage design optimizations to meet timing.
• Support silicon bring-up and tape-out with physical design expertise.
• Contribute to PD flows, automation scripts, and methodologies.

Education

BSc/MSc in Electronics Engineering or similar

Tools

Synopsys IC tools

Cadence IC tools

Flow development & setup

Job description

Nordic Semiconductor is hiring a Physical Design Engineer to transform advanced semiconductor designs into high-performance silicon. You will drive floorplanning, power integrity, and place-and-route, collaborating across design teams to ensure robust tape-out.

You will contribute to PD flow automation, analyze power integrity, and support silicon bring-up. This role values strong English communication and problem-solving in a fast-paced environment.